Vertical isolation in shallow n-well CMOS circuits

This letter examines vertical punchthrough in a shallow conventional n-well suitable for use in high-packing-density VLSI CMOS circuits. It is shown that full vertical isolation can be maintained even when the well beneath a p+ diffusion is completely depleted-that is the p+-to-n-well and n-well-to-p-substrate depletion regions meet-and that this offers an advantage in terms of p+ junction capacitance. However, if thin p-on-p+ epitaxial substrate material is used for latch-up suppression, then vertical isolation can be severely degraded. This effect ultimately limits the thickness of the epitaxial layer and hence the degree of latch-up protection.