Fault Tolerant ICAP Controller for High-Reliable Internal Scrubbing

High reliable reconfigurable applications today require system platforms that can easily and quickly detect and correct single event upsets. This capability, however, can be costly for FPGAs. This paper demonstrates a technique for detecting and repairing SEUs within the configuration memory of a Xilinx Virtex-4 FPGA using the ICAP interface. The internal configuration access port (ICAP) provides a port internal to the FPGA for configuring the FPGA device. An application note demonstrates how this port can be used for both error injection and scrubbing (L. Jones, 2007). We have extended this work to create a fault tolerant ICAP scrubber by triplicating the internal ICAP circuit using TMR and block memory scrubbing. This paper will describe the costs, benefits, and reliability of this fault-tolerant ICAP controller.

[1]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[2]  J. Maiz,et al.  Characterization of multi-bit soft error events in advanced SRAMs , 2003, IEEE International Electron Devices Meeting 2003.

[3]  R. Koga,et al.  SEU hardening of field programmable gate arrays (FPGAs) for space applications and device characterization , 1994 .

[4]  John Williams,et al.  Reconfigurable FPGAS for real time image processing in space , 2002, 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628).

[5]  M. Caffrey,et al.  Evaluating TMR Techniques in the Presence of Single Event Upsets , 2003 .

[6]  Jean-Didier Legat,et al.  Enabling certification for dynamic partial reconfiguration using a minimal flow , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Carl Carmichael,et al.  Triple Module Redundancy Design Techniques for Virtex FPGAs, Application Note 197 , 2001 .

[8]  M. Caffrey,et al.  Correcting single-event upsets through virtex partial configuration , 2000 .

[9]  Kris Gaj,et al.  Secure partial reconfiguration of FPGAs , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[10]  Pedro Reviriego,et al.  An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[11]  Lilian Bossuet,et al.  Dynamically configurable security for SRAM FPGA bitstreams , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[12]  Voicu Groza,et al.  A Self-Reconfigurable Platform for Built-In Self-Test Applications , 2007, IEEE Transactions on Instrumentation and Measurement.

[13]  K. Johansson,et al.  Neutron induced single-word multiple-bit upset in SRAM , 1999 .

[14]  C. Carmichael,et al.  A fault injection analysis of Virtex FPGA TMR design methodology , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).