Levo: IPC in the 10's via Resource Flow Computing

Many studies have concluded that typical programs (e.g., SPECint) contain a significant amount of Instruction Level Parallelism (ILP) for non-oracle assumptions. For example, Lam and Wilson[2] reported an ILP of about 40 for SP-CDMF (single path speculative execution with minimal control dependencies[3]). So why are academia and industry still working with single digit IPC’s? In short, nobody has been aggressive enough: issue widths are typically set to four instructions and advanced high-ILP techniques have not been used. One of the major problems faced by current designers is that none of the existing methods scales well and the required hardware is both complex and costly. The Levo machine model attempts to extract available

[1]  Monica S. Lam,et al.  Limits of control flow on parallelism , 1992, ISCA '92.

[2]  John G. Cleary,et al.  The architecture of an optimistic CPU: the WarpEngine , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[3]  Augustus K. Uht,et al.  A Theory of Reduced and Minimal Procedural Dependencies , 1991, IEEE Trans. Computers.

[4]  Thomas F. Wenisch,et al.  IPC in the 10s via Resource Flow Computing with Levo , 2001 .