Special Session: Delay Fault Testing - Present and Future

This article presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this maturing field for new technologies, signal integrity, process variations, faster than critical path operation, asynchronous circuits, counterfeit ICs, and hardware Trojans. This information is compiled to provide direction to students, practicing engineers, and researchers alike.

[1]  Pablo Moscato,et al.  Handbook of Applied Optimization , 2000 .

[2]  Michele Favalli.  A fuzzy model for path delay fault detection , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Zainalabedin Navabi,et al.  A novel SAT-based ATPG approach for transition delay faults , 2017, 2017 IEEE International High Level Design Validation and Test Workshop (HLDVT).

[4]  Vishwani D. Agrawal,et al.  An efficient automatic test generation system for path delay faults in combinational circuits , 1995, Proceedings of the 8th International Conference on VLSI Design.

[5]  Anzhela Yu. Matrosova,et al.  ROBDD based path delay fault testable combinational circuit synthesis , 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

[6]  Vishwani D. Agrawal,et al.  Modeling and test generation for combinational hardware Trojans , 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

[7]  Janak H. Patel,et al.  Segment delay faults: a new fault model , 1996, Proceedings of 14th VLSI Test Symposium.

[8]  Haihua Yan,et al.  Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[9]  Bernd Becker,et al.  Variation-Aware Fault Grading , 2012, 2012 IEEE 21st Asian Test Symposium.

[10]  Kwang-Ting Cheng,et al.  Generation of High Quality Non-Robust Tests for Path Delay Faults , 1994, 31st Design Automation Conference.

[11]  Yi Liu,et al.  Harzard-Based ATPG for Improving Delay Test Quality , 2015, J. Electron. Test..

[12]  Cecilia Metra,et al.  New Design for Testability Approach for Clock Fault Testing , 2012, IEEE Transactions on Computers.

[13]  Jie Li,et al.  At-speed delay characterization for IC authentication and Trojan Horse detection , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[14]  Raed Mesleh,et al.  A comprehensive study and analysis on SAT-solvers: advances, usages and achievements , 2018, Artificial Intelligence Review.

[15]  Kwang-Ting Cheng,et al.  On testing the path delay faults of a microprocessor using its instruction set , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[16]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[17]  Elena Gramatová,et al.  Delay Fault Coverage Increasing in Digital Circuits , 2013, 2013 Euromicro Conference on Digital System Design.

[18]  Fareena Saqib,et al.  Detecting Hardware Trojans Using Delay Analysis , 2018 .

[19]  Michael Pabst,et al.  RESIST: a recursive test pattern generation algorithm for path delay faults , 1994, EURO-DAC '94.

[20]  Shi-Yu Huang,et al.  AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

[21]  Mark Zwolinski,et al.  Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[22]  Yu Huang.  On N-detect pattern set optimization , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[23]  Mark Mohammad Tehranipoor,et al.  Timing-based delay test for screening small delay defects , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[24]  Mark Mohammad Tehranipoor,et al.  Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead , 2014, J. Electron. Test..

[25]  Narendra Devta-Prasanna,et al.  Effective and Efficient Test Pattern Generation for Small Delay Defect , 2009, 2009 27th IEEE VLSI Test Symposium.

[26]  Ivan E. Sutherland,et al.  The tyranny of the clock , 2012, Commun. ACM.

[27]  Daniel G. Saab,et al.  Automatic Generation of Instructions to Robustly Test Delay Defects in Processors , 2007, 12th IEEE European Test Symposium (ETS'07).

[28]  Nor Hisham Hamid,et al.  Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram , 2014, 2014 5th International Conference on Intelligent and Advanced Systems (ICIAS).

[29]  Huawei Li,et al.  GPU-accelerated fault simulation and its new applications , 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

[30]  Milos Krstic,et al.  A survey about testing asynchronous circuits , 2015, 2015 European Conference on Circuit Theory and Design (ECCTD).

[31]  Chang Liu,et al.  FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects , 2014, 2014 International Test Conference.

[32]  Adit D. Singh,et al.  Exploiting path delay test generation to develop better TDF tests for small delay defects , 2017, 2017 IEEE International Test Conference (ITC).

[33]  Kwang-Ting Cheng,et al.  Delay testing considering power supply noise effects , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[34]  Sachin S. Sapatnekar,et al.  Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.

[35]  M. C. Bhuvaneswari,et al.  Delay Fault Testing of VLSI Circuits , 2018, Test Generation of Crosstalk Delay Faults in VLSI Circuits.

[36]  Bernd Becker,et al.  Small-delay-fault ATPG with waveform accuracy , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[37]  Jacob Savir,et al.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[38]  Michael S. Hsiao,et al.  A novel statistical and circuit-based technique for counterfeit detection in existing ICs , 2013, ACM Great Lakes Symposium on VLSI.

[39]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[40]  Rolf Drechsler,et al.  As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization , 2011, 2011 Design, Automation & Test in Europe.

[41]  Adit D. Singh,et al.  Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths , 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

[42]  Rolf Drechsler,et al.  High Quality Test Pattern Generation and Boolean Satisfiability , 2012 .

[43]  Irith Pomeranz,et al.  Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[44]  Abhijit Chatterjee,et al.  A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays , 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

[45]  Vishwani D. Agrawal,et al.  The path-status graph with application to delay fault simulation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[46]  B. I. Devadas,et al.  Design for testability : Using scanpath techniques for path-delay test and measurement , 1991 .

[47]  Mark Mohammad Tehranipoor,et al.  Test and Diagnosis for Small-Delay Defects , 2011 .

[48]  Susanta Chakraborty,et al.  Synthesis of symmetric functions for path-delay fault testability , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[49]  Yu Zheng,et al.  SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[50]  Robert B. Hitchcock,et al.  Timing Verification and the Timing Analysis Program , 1982, 19th Design Automation Conference.

[51]  John A. Waicukauski,et al.  On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[52]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[53]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[54]  Paul Penfield,et al.  Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.

[55]  Nur A. Touba.  X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR , 2007, 2007 IEEE International Test Conference.

[56]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[57]  Michael S. Hsiao,et al.  High quality atpg for delay defects , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[58]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[59]  Gaetano Borriello,et al.  Testing asynchronous circuits: A survey , 1995, Integr..

[60]  Hans-Joachim Wunderlich,et al.  Multi-level timing simulation on GPUs , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[61]  Hans-Joachim Wunderlich,et al.  Optimized Selection of Frequencies for Faster-Than-at-Speed Test , 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

[62]  Sachin S. Sapatnekar,et al.  Timing Analysis and Optimization of Sequential Circuits , 1998 .

[63]  Vishwani D. Agrawal.  Synchronous Path Analysis in MOS Circuit Simulator , 1982, 19th Design Automation Conference.

[64]  Soumitra Bose,et al.  Delay fault simulation with bounded gate delay mode , 2007, 2007 IEEE International Test Conference.

[66]  Hassan Ghasemzadeh,et al.  Fault modeling in controllable polarity silicon nanowire circuits , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[67]  Eby G. Friedman,et al.  Ramp Input Response of RC Tree Networks , 1996 .

[68]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[69]  Mark Mohammad Tehranipoor,et al.  Low-cost on-chip structures for combating die and IC recycling , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[70]  Nur A. Touba,et al.  Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[71]  Vishwani D. Agrawal,et al.  Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests , 1997, J. Electron. Test..

[72]  Vishwani D. Agrawal,et al.  False-path removal using delay fault simulation , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[73]  Ujjwal Guin,et al.  Counterfeit Integrated Circuits: Detection and Avoidance , 2015 .

[74]  Kwang-Ting Cheng,et al.  Delay testing considering crosstalk-induced effects , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[75]  Mark Mohammad Tehranipoor,et al.  Path-delay fingerprinting for identification of recovered ICs , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[76]  Haihua Yan,et al.  Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study , 2004, 2004 International Conferce on Test.

[77]  Hyunki Kim,et al.  Low-cost gate-oxide early-life failure detection in robust systems , 2010, 2010 Symposium on VLSI Circuits.

[78]  Xiaoqing Wen,et al.  GPU-accelerated small delay fault simulation , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[79]  Nilanjan Mukherjee,et al.  On Compaction Utilizing Inter and Intra-Correlation of Unknown States , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[80]  Michael John Sebastian Smith,et al.  Application-specific integrated circuits , 1997 .

[81]  Mark Mohammad Tehranipoor,et al.  A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[82]  Sybille Hellebrand,et al.  Design for Small Delay Test - A Simulation Study , 2018, Microelectron. Reliab..

[83]  Michael S. Hsiao,et al.  Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors , 2003, J. Electron. Test..

[84]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[85]  Krishnendu Chakrabarty,et al.  Delay Test and Small-Delay Defects , 2011 .

[86]  Richard Putman,et al.  Enhanced timing-based transition delay testing for small delay defects , 2006, 24th IEEE VLSI Test Symposium.

[87]  Jeff Rearick.  Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[88]  T. I. Kirkpatrick,et al.  PERT as an aid to logic design , 1966 .

[89]  Feng Shi,et al.  Testing Delay Faults in Asynchronous Handshake Circuits , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[90]  Irith Pomeranz,et al.  A novel method of improving transition delay fault coverage using multiple scan enable signals , 2005, 2005 International Conference on Computer Design.

[91]  Hiroshi Takahashi,et al.  Fault simulation and test generation for clock delay faults , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[92]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[93]  Sandip Kundu.  An incremental algorithm for identification of longest (shortest) paths , 1994, Integr..

[94]  Xiaoqing Wen,et al.  GPU-Accelerated Simulation of Small Delay Faults , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[95]  Kwang-Ting Cheng,et al.  Test program synthesis for path delay faults in microprocessor cores , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[96]  Krishnendu Chakrabarty,et al.  Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization , 2012, 2012 IEEE 21st Asian Test Symposium.

[97]  Dong Hyun Baik,et al.  Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[98]  Vishwani D. Agrawal,et al.  Two-Pattern ∆IDDQ Test for Recycled IC Detection , 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

[99]  Vishwani D. Agrawal,et al.  Delay fault models and coverage , 1998, Proceedings Eleventh International Conference on VLSI Design.

[100]  Sandeep K. Gupta,et al.  Trojan detection via delay measurements: A new approach to select paths and vectors to maximize effectiveness and minimize cost , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[101]  Bernd Becker,et al.  Towards Variation-Aware Test Methods , 2011, 2011 Sixteenth IEEE European Test Symposium.

[102]  Michael H. Schulz,et al.  DYNAMITE: an efficient automatic test pattern generation system for path delay faults , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[103]  Yiorgos Makris,et al.  Hardware Trojan detection using path delay fingerprint , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[104]  Hans-Joachim Wunderlich,et al.  High-Throughput Logic Timing Simulation on GPGPUs , 2015, TODE.

[105]  Adit D. Singh,et al.  Distinguishing Resistive Small Delay Defects from Random Parameter Variations , 2010, 2010 19th IEEE Asian Test Symposium.

[106]  Adit D. Singh,et al.  Detection conditions for errors in self-adaptive better-than-worst-case designs , 2014, 2014 19th IEEE European Test Symposium (ETS).

[107]  M. Ray Mercer,et al.  Statistical delay fault coverage and defect level for delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[108]  Irith Pomeranz,et al.  Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[109]  Mark Mohammad Tehranipoor,et al.  Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[110]  Toshiyuki Maeda,et al.  Invisible delay quality - SDQM model lights up what could not be seen , 2005, IEEE International Conference on Test, 2005..

[111]  Vishwani D. Agrawal,et al.  On test coverage of path delay faults , 1996, Proceedings of 9th International Conference on VLSI Design.

[112]  Walter Anheier,et al.  Quality Determination for Gate Delay Fault Tests Considering Three-State Elements , 1999, J. Electron. Test..

[113]  Enamul Amyeen,et al.  Evaluation of the quality of N-detect scan ATPG patterns on a processor , 2004, 2004 International Conferce on Test.

[114]  Michel Laurence.  Introduction to Octasic Asynchronous Processor Technology , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[115]  Shi-Yu Huang,et al.  Circuit and Methodology for Testing Small Delay Faults in the Clock Network , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[116]  Michael D. Ciletti,et al.  A variable observation time method for testing delay faults , 1991, DAC '90.

[117]  Yvon Savaria,et al.  Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits , 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

[118]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[119]  Prithviraj Banerjee.  Parallel algorithms for VLSI computer-aided design , 1994 .

[120]  Régis Leveugle,et al.  Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic , 2006, IEEE Transactions on Computers.

[121]  N. Ahmed,et al.  A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[122]  Michele Favalli,et al.  A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[123]  Adit D. Singh,et al.  An output compression scheme for handling X-states from over-clocked delay tests , 2010, 2010 28th VLSI Test Symposium (VTS).

[124]  Endre Boros,et al.  Pseudo-Boolean optimization , 2002, Discret. Appl. Math..

[125]  Haihua Yan,et al.  Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study , 2004 .

[126]  Mark Mohammad Tehranipoor,et al.  Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain , 2014, Proceedings of the IEEE.

[127]  Michael H. Schulz,et al.  Advanced automatic test pattern generation techniques for path delay faults , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.