A 60 mW per lane, 4 x 23-Gb/s 27-1 PRBS generator

An ultra-low-power, 2 7 -1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz f T SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method.

[1]  T. Link,et al.  2-1 SiGe PRBS Generator IC up to 86 Gbit/s , 2005 .

[2]  Y. Amamiya,et al.  1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit , 2003, 25th Annual Technical Digest 2003. IEEE Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003..

[3]  Behzad Razavi.  Design of intergrated circuits for optical communications , 2002 .

[4]  R. Beerkens,et al.  A comparison of Si CMOS, SiGe BiCMOS, and InP HBT technologies for high-speed and millimeter-wave ICs , 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

[5]  Hans-Dieter Wohlmuth,et al.  A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[6]  P. Chevalier,et al.  230 GHz self-aligned SiGeC HBT for 90 nm BiCMOS technology , 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.

[7]  A. Ebberg,et al.  Generation of high-speed pseudorandom sequences using multiplex-techniques , 1996 .

[8]  S.P. Voinigescu,et al.  A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic , 2005, IEEE Journal of Solid-State Circuits.

[9]  H. Veenstra.  1-58 Gb/s PRBS generator with <1.1 ps RMS jitter in InP technology , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[10]  B. Karajica,et al.  An 80-Gb/s 2/sup 31/-1 pseudorandom binary sequence generator in SiGe BiCMOS technology , 2005, IEEE Journal of Solid-State Circuits.

[11]  D. Yamazaki,et al.  40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[12]  D. Kucharski,et al.  A 40 Gb/s 2.5 V 2/sup 7/-1 PRBS generator in SiGe using a low-voltage logic family , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  A. N. V. Luyn.  Shift-register connections for delayed versions of m-sequences , 1978 .

[14]  Mounir Meghelli,et al.  45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence] , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[15]  Kevin T. Kornegay,et al.  SiGe Using a Low-Voltage Logic Family , 2005 .

[16]  R. Malasani,et al.  A SiGe 10-Gb/s multi-pattern bit error rate tester , 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.

[17]  J. O'Reilly.  Series-parallel generation of m-sequences , 1975 .

[18]  D. Celi,et al.  230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications , 2005, IEEE Journal of Solid-State Circuits.

[19]  S.P. Voinigescu,et al.  The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks , 2006, IEEE Journal of Solid-State Circuits.

[20]  S.P. Voinigescu,et al.  30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits , 2005, IEEE Transactions on Microwave Theory and Techniques.

[21]  Josef Bock,et al.  100-Gb/s 27-1 and 54-Gb/s 211- 1 PRBS generators in sige bipolar technology , 2004 .

[22]  Sorin P. Voinigescu,et al.  Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[23]  S.I. Long,et al.  Design analysis and circuit enhancements for high-speed bipolar flip-flops , 2005, IEEE Journal of Solid-State Circuits.

[24]  J.K. Notthoff,et al.  A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology , 1999, IEEE Journal of Solid-State Circuits.

[25]  Solomon W. Golomb,et al.  Shift Register Sequences , 1981 .

[26]  Thomas H. Lee.  The Design of CMOS Radio-Frequency Integrated Circuits , 1998 .

[27]  J. Bock,et al.  Silicon bipolar IC for PRBS testing generates adjustable bit rates up to 25 Gbit/s , 1997 .

[28]  G. Hanke,et al.  A 10 Gb/s silicon bipolar IC for PRBS testing , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[29]  W. J. McFarland,et al.  1-Gword/s pseudorandom word generator , 1989 .

[30]  U. Langmann,et al.  PRBS generation and error detection above 10 Gb/s using a monolithic Si bipolar IC , 1994 .