Planar topological routing of pad nets

Abstract This paper discusses the problem of single-layer topological routing of pad nets. A pad net is one that connects a set of module pins to a pad on the boundary of the chip. An important application arises in VLSI designs with many different power sources, in which case there may be multiple power and ground nets to be routed on a single layer. We present an O(n) algorithm for checking the feasibility of a single-layer routing of pad nets, and an O(m × n) algorithm for constructing a planar topological routing, where n is the total number of pad-net pins on all the modules, and m is the number of modules. The feasibility algorithm exploits the special structure of the problem, and is based on a distribution sorting technique rather than being a general planarity checking algorithm. The topological routing algorithm first forms a chain of the modules, and then performs a permutation routing of the nets using the chain as a guide.

[1]  Ron Y. Pinter,et al.  An algorithm for the optimal placement and routing of a circuit within a ring of pads , 1983, 24th Annual Symposium on Foundations of Computer Science (sfcs 1983).

[2]  Charles E. Leiserson,et al.  Algorithms for routing and testing routability of planar VLSI layouts , 1985, STOC '85.

[3]  Malgorzata Marek-Sadowska,et al.  Single-Layer Routing for VLSI: Analysis and Algorithms , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  R. Y. Pinter,et al.  THE IMPACT OF LAYER ASSIGNMENT METHODS ON LAYOUT ALGORITHM FOR INTEGRATED CIRCUITS , 1983 .

[5]  Robert E. Tarjan,et al.  Efficient Planarity Testing , 1974, JACM.

[6]  Anderew S. Moulton.  Laying the Power and Ground Wires on a VLSI Chip , 1983, 20th Design Automation Conference Proceedings.

[7]  Fabrizio Luccio,et al.  A Visibility Problem in VLSI Layout Compaction , 1984 .