论文信息 - Performance Analysis of Low Power CSVCO for PLL Architecture

Performance Analysis of Low Power CSVCO for PLL Architecture

This paper describes the performance analysis of an ultra low power, low phase noise current starved CMOS VCO for PLL architecture. This CSVCO is applicable for PLL application such as in, frequency control, frequency multipliers, tracking generators, clock generation and recovery etc. Transient response and phase noise analysis of CSVCO is performed and after simulation the phase noise at 1MHz is-104.0dBc/Hz with supply voltage of 1 V with a centre frequency of 2GHz. It is performed using cadence virtuoso gpdk045 nm CMOS technology.

Vijay Nath | Suraj Kumar Saw

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