A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC

This brief presents a 0.9-V 8-bit 800-MS/s energy-efficient two-step successive-approximation register (SAR) analog-to-digital converter (ADC) without an inter-stage residue amplifier. A charge-sharing technique is used to avoid large static current consumption of the residue amplifier and to eliminate the distortion caused by insufficient amplifier output headroom. Besides, a self-triggered latch technique not only saves the digital power but also accelerates the conversion speed by reducing the SAR loop loading. The prototype ADC consumes 1.59 mW at 800 MS/s and achieves a Nyquist signal-to-noise and distortion ratio of 45.8 dB in 40-nm CMOS technology. It results in an figure of merit of 12.5 fJ/c.-s.

[1]  Ho-Jin Park,et al.  A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC , 2015, IEEE Journal of Solid-State Circuits.

[2]  Hsin-Shu Chen,et al.  A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Yusuf Leblebici,et al.  22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[4]  Yuriy Greshishchev,et al.  A 24GS/s 6b ADC in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Chung-Ming Huang,et al.  A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[6]  Franziska Hoffmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[7]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[8]  Rui Paulo Martins,et al.  A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[9]  Franco Maloberti,et al.  A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation , 2012, IEEE Journal of Solid-State Circuits.

[10]  Yuan-Ching Lien,et al.  A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[11]  Samuel Palermo,et al.  A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS , 2013, 2013 Symposium on VLSI Circuits.

[12]  Han Yan,et al.  11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[13]  Yun Chiu,et al.  A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer , 2017, IEEE Journal of Solid-State Circuits.

[14]  Yusuf Leblebici,et al.  A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS , 2013, 2013 Symposium on VLSI Circuits.

[15]  Qiang Li,et al.  An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Patrick Chiang,et al.  A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[17]  Yusuf Leblebici,et al.  A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS , 2013, IEEE Journal of Solid-State Circuits.

[18]  Michael P. Flynn,et al.  A SAR-Assisted Two-Stage Pipeline ADC , 2011, IEEE Journal of Solid-State Circuits.