An Efficient Zigzag Scanning and Entropy Coding Architecture Design

Rate distortion optimization (RDO) technique is the best known mode decision method in recent video coding standard, such as H.264 and AVS. However, the unbearable computational burden limits its application. According to the proposed block-level pipeline architecture of RDO-based MD, we find that zigzag scanning and entropy coding are the bottlenecks. In our paper, we firstly analyze the time consumption of the bottlenecks, and then we propose our efficient zigzag scanning and entropy coding architecture. Finally, our enhanced architecture is implemented in AVS encoder. The experimental results show that 20% throughput can be increased compared with the 4-way parallel scanning and entropy coding. With the proposed architecture, the real time RDO-based MD processing of [email protected] can be supported. And our design is realized in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18μm CMOS technology with 50K logic gates and 6 KB SRAMs at 237MHZ operation frequency.

[1]  Hitoshi Kiya,et al.  Advances in Multimedia Information Processing - PCM 2010 - 11th Pacific Rim Conference on Multimedia, Shanghai, China, September 2010, Proceedings, Part II , 2011, Pacific Rim Conference on Multimedia.

[2]  Guifen Tian,et al.  High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction , 2008, 2008 International Conference on Communications, Circuits and Systems.

[3]  Wen Gao,et al.  Fast Mode Decision Based on RDO for AVS High Definition Video Encoder , 2010, PCM.

[4]  Xin Tong,et al.  A novel fast DCT coefficient scan architecture , 2009, 2009 Picture Coding Symposium.

[5]  Wen Gao,et al.  Multi-stage motion vector prediction schedule strategy for AVS HD encoder , 2010, 2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE).

[6]  Liang-Gee Chen,et al.  Hardware architecture design for H.264/AVC intra frame coder , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[7]  Wen Gao,et al.  Low complexity RDO mode decision based on a fast coding-bits estimation model for H.264/AVC , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[8]  Susanto Rahardja,et al.  Fast mode decision algorithm for intraprediction in H.264/AVC video coding , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[9]  Honggang Qi,et al.  Hardware Friendly Mode Decision Algorithm for High Definition AVS Video Encoder , 2009, 2009 2nd International Congress on Image and Signal Processing.