Massively Parallel Processor Architectures for Resource-aware Computing

We present a class of massively parallel processor architectures called invasive tightly coupled processor arrays (TCPAs). The presented processor class is a highly parame- terizable template, which can be tailored before runtime to fulfill costumers' requirements such as performance, area cost, and energy efficiency. These programmable accelerators are well suited for domain-specific computing from the areas of signal, image, and video processing as well as other streaming processing applications. To overcome future scaling issues (e.g., power con- sumption, reliability, resource management, as well as application parallelization and mapping), TCPAs are inherently designed in a way to support self-adaptivity and resource awareness at hardware level. Here, we follow a recently introduced resource- aware parallel computing paradigm called invasive computing where an application can dynamically claim, execute, and release resources. Furthermore, we show how invasive computing can be used as an enabler for power management. Finally, we will introduce ideas on how to realize fault-tolerant loop execution on such massively parallel architectures through employing on- demand spatial redundancies at the processor array level. I. INTRODUCTION The steady miniaturization of feature sizes allows to create increasingly complex Multi-Processor System-on-Chip (MP- SoC) architectures but raises also numerous questions. These challenges include imperfections and unreliability of the de- vices as well as scalability problems of the architectures, as for instance, how an optimal communication topology or memory architecture should look like. The situation is even more severe with respect to power consumption because chips can handle only a limited power budget—but technology shrinking leads also to higher energy densities continuously. As a consequence, the potentially available chip area might not be fully utilized or at least not simultaneously. These phenomena are also known as power wall and utilization wall (1). Other scalability issues, caused by the sheer complexity of exponential growth, are related to resource management as well as parallelization and mapping approaches. This leads to the following conclusion: Future systems will only scale if the mapping and runtime methods will considerably improve—this reasoning holds for both embedded and portable devices such as smartphones and tablets as well as large scale systems as used for high- performance computing. Customization and heterogeneity in the form of domain-specific components such as accelerators are the key to success for future performance gains (2).