A low power monolithic subsampled phase-locked loop architecture for wireless transceivers

A subsampling stage driven by a crystal reference eliminates the prescaler and greatly reduces the division ratio of the PLL. The wide bandwidth of the loop inhibits the VCO phase-noise, allowing for the use of on-chip VCOs. The resulting architecture is particularly suitable for DDS-driven PLL architectures since it relaxes the requirements on the DDS thus further reducing the power consumption. The advantages of the architecture are highlighted and system- and circuit-level simulations are presented.