Fixed Polarity Reed-Muller Network Synthesis and Its Application in AND-OR/XOR-based Circuit Realization with Area-Power Trade-off

Abstract Though AND-OR and AND-XOR logic based minimization of combinational functions are well studied areas in the domain of very large scale integrated (VLSI) circuit synthesis, most of the real-life multi-output functions are a mix of OR and XOR dominated subfunctions. A judicious choice of OR and XOR decomposition strategy can thus result in the best possible realization of these. This paper explores this avenue and establishes the area-power trade-off existing in such a mixed synthesis approach. It shows on an average upto 16.91% improvement in area and upto 15.60% improvement in power over the AND-OR based logic minimization.

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