Modular cube-connected cycle architecture for efficiet image processing (abstract and references only)

Processor array of regular interconnection topology can achieve a high performance by concurrently processing and interchanging data. This system is thus effective for the problems where a large amount data need to be fastly processed. Image processing such as image transformation and template matching is one of the typical examples. Here the two-dimensional data manipulation requires a substantially large number of processing elements(PEs) and simple regular interconnection topology. This nature results in the VLSI processor arrays to be a practical solution to this problem. To quickly process the image data, a large number of multiprocessor architectures and corresponding parallel algorithms have been proposed in the literature. Among them, the hypercube network has shown to be one of the most efficient architectures for parallel processing. Recently, Ranka and Sahni[1] developed an efficient scheme which can transform a gray scale N × N image in O(logN) time using an N ~ node hypercube network, while a uniprocessor system requires O(2 N) time. However, the main drawback of the hypercube network is its inefficiency for VLSI /WSI implementation. This is because the number of interconnection edges of the hypercube network grows exponentially (O(N2JV)) along the number of PEs in the network(N). Note that N is very large for image processing. Thus the chip area (f~(N2)) and maximum edge length overhead due to interconnection will be significant. Furthermore, efficient fault tolerance scheme essential for VLSI/WSI systems to enhance the yield and reliability is difficult to be developed. To solve this problem, a parallel architecture which is much more efficient for VLSI implementation than hypercube is proposed. The proposed architecture is constructed by connecting some modules where each module is a Cube-Connected Cycles(CCC). We call it MCCC(Modular CCC)[2]. The MCCC network performs as efficient as hypercube using O(log2n) less chip area. It is mainly due to its degree boundness as three. Efficient fault tolerance scheme is also much easier to develop. The proposed MCCC(m,h) network can be described as follows.