Switching constraint-driven thermal and reliability analysis of Nanometer designs

As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors in the latest 32nm processes, interconnect wear-out via electromigration is as critical a design parameter, if not more so, as timing, power, and area, and must be planned for from the outset. This paper presents a true three-dimensional thermal analysis in order to accurately transform power dissipation into a temperature profile for more accurate reliability estimation at the level of interconnect metal, via resistors and device fingers. This enhancement to prior electromigration analysis flows was a critical enabling technology for deep sub-micron microprocessor design, and will prove only more essential as process technology continues to shrink, and electromigration constraints become ever more restrictive. In addition, the thermal analysis enabled better prediction of device reliability, which we can now calculate and measure the impact of, at the block-level.

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