Concatenated Reed-Solomon Code with Hamming Code for DRAM Controller

In this paper, we propose a concatenated Reed-Solomon code with a Hamming code for dynamic random access memory (DRAM) controller. The concatenated code consists of a Reed-Solomon outer code, two shortened Reed-Solomon codes, and a Hamming inner code. The proposed code takes the advantages of Reed-Solomon codes and Hamming codes to protect DRAM memory data against single event upsets and multiple bit upsets. At the byte error rate of 10-7, the proposed decoder shows about 1.3 dB of coding gain over that of the conventional Reed-Solomon decoder. We implement the proposed concatenated Reed-Solomon code on a very large-scale integration (VLSI) chip with 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library at a supply voltage of 1.2 V. The core area of proposed architecture is 1.12 mm2 with the gate counts of 121,900. The synthesized result shows the maximum throughput of 1.71 Gbps and the measured power consumption of 69 mW at 259 MHz.

[1]  Seungpum Kang,et al.  ASIC Implementation of Reed-Solomon Error Correction Circuits for Low Area Overhead on Memory System , 2008 .

[2]  Martin Bossert,et al.  Collaborative Decoding of Interleaved Reed–Solomon Codes and Concatenated Code Designs , 2009, IEEE Transactions on Information Theory.

[3]  Richard W. Hamming,et al.  Coding and Information Theory , 1980 .

[4]  L. Carro,et al.  Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

[5]  Xin-Yu Shih,et al.  A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[6]  Ricardo Reis,et al.  An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories , 2005, IEEE Design & Test of Computers.

[7]  In-Cheol Park,et al.  Loosely coupled memory-based decoding architecture for low density parity check codes , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  R. Reed,et al.  Heavy ion and proton-induced single event multiple upset , 1997 .

[9]  P. Chaichanavong,et al.  On the Concatenation of Soft Inner Code With Reed–Solomon Code for Perpendicular Magnetic Recording , 2007, IEEE Transactions on Magnetics.

[10]  Meng Zhang,et al.  VLSI implementation and optimization design of Reed-Solomon decoder in QAM demodulation chip , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[11]  Luigi Carro,et al.  A multiple bit upset tolerant SRAM memory , 2003, TODE.

[12]  In-Cheol Park,et al.  SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Luca Fanucci,et al.  A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

[14]  Stephen G. Wilson,et al.  Digital Modulation and Coding , 1995 .