Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated
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Hai Wei | H.-S. Philip Wong | Lan Wei | Nishant Patil | Subhasish Mitra | Albert Lin | Max M. Shulaker | Hong-Yu Chen | Jie Zhang
[1] Hai Wei,et al. Linear increases in carbon nanotube density through multiple transfer technique. , 2011, Nano letters.
[2] Hai Wei,et al. Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits , 2010, 2010 Symposium on VLSI Technology.
[3] Jie Deng,et al. Modeling and Performance Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and Screening Effect , 2008, IEEE Transactions on Nanotechnology.
[4] Hai Wei,et al. VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[5] Pornsak Srisungsitthisunti,et al. Measurement of metal/carbon nanotube contact resistance by adjusting contact length using laser ablation , 2008, Nanotechnology.
[6] Ali Javey,et al. Graphitic interfacial layer to carbon nanotube for low electrical contact resistance , 2010, 2010 International Electron Devices Meeting.
[7] J. Rogers,et al. Improved Density in Aligned Arrays of Single‐Walled Carbon Nanotubes by Sequential Chemical Vapor Deposition on Quartz , 2010, Advanced materials.
[8] Hai Wei,et al. ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration , 2009, IEEE Transactions on Electron Devices.
[9] P. Ashburn,et al. Numerically Efficient Modeling of CNT Transistors With Ballistic and Nonballistic Effects for Circuit Simulation , 2010, IEEE Transactions on Nanotechnology.
[10] Hai Wei,et al. Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[11] P. Avouris,et al. Carbon-based electronics. , 2007, Nature nanotechnology.
[12] Nishant Patil,et al. Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] H.-S. Philip Wong,et al. Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Hai Wei,et al. Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes , 2011, IEEE Transactions on Nanotechnology.
[15] Giovanni De Micheli,et al. Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement , 2010, Design Automation Conference.
[16] M. Lundstrom,et al. Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistors , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[17] Nishant Patil,et al. Carbon Nanotube circuits in the presence of carbon nanotube density variations , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[18] E. Pop,et al. Thermal conductance of an individual single-wall carbon nanotube above room temperature. , 2005, Nano letters.
[19] H.-S. Philip Wong,et al. Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[20] Ashok Srivastava,et al. Current transport modeling of carbon nanotube field effect transistors , 2009 .
[21] H.-S. Philip Wong,et al. Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications , 2010, 2010 International Electron Devices Meeting.
[22] T. Zimmer,et al. Computationally Efficient Physics-Based Compact CNTFET Model for Circuit Design , 2008, IEEE Transactions on Electron Devices.
[23] K. Roy,et al. Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits , 2009, IEEE Transactions on Electron Devices.
[24] Albert Lin,et al. Current Scaling in Aligned Carbon Nanotube Array Transistors With Local Bottom Gating , 2010, IEEE Electron Device Letters.
[25] John A. Rogers,et al. Improved Synthesis of Aligned Arrays of Single-Walled Carbon Nanotubes and Their Implementation in Thin Film Type Transistors† , 2007 .
[26] P. Avouris,et al. Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown , 2001, Science.
[27] Hongjie Dai,et al. Alkaline metal-doped n-type semiconducting nanotubes as quantum dots , 2000 .
[28] Shinobu Fujita,et al. Modeling and analysis of circuit performance of ballistic CNFET , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[29] H. Wong,et al. Analytical ballistic theory of carbon nanotube transistors: Experimental validation, device physics, parameter extraction, and performance projection , 2008 .
[30] H.-S. Philip Wong,et al. A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[31] P. Solomon,et al. Contact Resistance to a One-Dimensional Quasi-Ballistic Nanotube/Wire , 2011, IEEE Electron Device Letters.
[32] T Mizutani,et al. Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges , 2010, Nanotechnology.
[33] Yu Cao,et al. Compact modeling of carbon nanotube transistor for early stage process-design exploration , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).
[34] H.-S. Philip Wong,et al. Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[35] Jie Zhang,et al. Robust System Design , 2010, 2010 23rd International Conference on VLSI Design.
[36] H.-S. Philip Wong,et al. Carbon nanotube circuits: Living with imperfections and variations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[37] S. Wong,et al. Monolithic 3D Integrated Circuits , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).