Spur suppression technique for multiplied delay locked loop
暂无分享,去创建一个
[1] Sander Gierkink. A 1V 15.6mW 1–2GHz −119dBc/Hz @ 200kHz clock multiplying DLL , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[2] Ian Galton,et al. Techniques for in-band phase noise suppression in re-circulating DLLs , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[3] I. Galton,et al. Techniques for phase noise suppression in recirculating DLLs , 2004, IEEE Journal of Solid-State Circuits.
[4] B.M. Helal,et al. A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance , 2008, IEEE Journal of Solid-State Circuits.
[5] Tad A. Kwasniewski,et al. A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[6] P. C. Maulik,et al. A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$ m CMOS With ${-}$70 dBc Reference Spur , 2007, IEEE Journal of Solid-State Circuits.
[7] Keng-Jan Hsiao,et al. The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning , 2008, IEEE Journal of Solid-State Circuits.
[8] William J. Dally,et al. A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips , 2002, IEEE J. Solid State Circuits.