GlYFF: A Framework for Global Yield and

Diminishing yields for modern CMOS and emerging technologies have become a major growing con- cern for IC manufacturers due to its direct impact on revenue. To this end, "Design for Yield (DFY)" have been proposed to proactively address manufacturing yield issues in the system design stage. While many DFY approaches have been developed for caches, GPUs and CPUs, they remain decoupled from each other, which is not ideal for modern microprocessors or MPSoCs that integrate multiple components onto a single die. In this paper we introduce "Global Yield and Floorplan Aware Design Optimization Framework (GlYFF)", a holistic computer- aided DFY framework that unifies redundancy based yield- centric design optimizations and floorplanning for MP- SoCs. GlYFF recognizes the different yield enhancement strategies for different on-die components, and is able to output detailed floorplans for accurate area/performance measurements. We demonstrate that compared to a seg- regated DFY methodology, GlYFF can achieve ~20% improvement in yield-per-area, a metric strongly correlated to revenue.

[1]  Mohammad Mirza-Aghatabar,et al.  SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement , 2009, 2009 Asian Test Symposium.

[2]  D. Weiss,et al.  The on-chip 3 MB subarray based 3rd level cache on an Itanium microprocessor , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[3]  Lars Liebmann,et al.  TCAD development for lithography resolution enhancement , 2001, IBM J. Res. Dev..

[4]  Yue Gao,et al.  A new paradigm for trading off yield, area and performance to enhance performance per wafer , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Eric Cheng,et al.  Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study , 2013, 2013 IEEE International Test Conference (ITC).

[6]  Yervant Zorian,et al.  Guest Editors' Introduction: Design for Yield and Reliability , 2004, IEEE Des. Test Comput..

[7]  Robert E. Lyons,et al.  The Use of Triple-Modular Redundancy to Improve Computer Reliability , 1962, IBM J. Res. Dev..

[8]  Mohammad Mirza-Aghatabar,et al.  Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[9]  Sandeep K. Gupta,et al.  A systematic methodology to improve yield per area of highly-parallel CMPs , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[10]  Seung-Moon Yoo,et al.  FlexRAM: Toward an advanced Intelligent Memory system , 1999, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[11]  Mohammad Mirza-Aghatabar,et al.  HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC , 2010, 2010 19th IEEE Asian Test Symposium.

[12]  V. Pitchumani,et al.  Design for manufacturability , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[13]  Hai Zhou,et al.  Yield-Aware Cache Architectures , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[14]  Qiang Xu,et al.  Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology , 2008, 2008 Design, Automation and Test in Europe.

[15]  J. A. Cunningham.  The use and evaluation of yield models in integrated circuit manufacturing , 1990 .

[16]  Kwang-Ting Cheng,et al.  A Cost Analysis Framework for Multi-core Systems with Spares , 2008, 2008 IEEE International Test Conference.

[17]  Sarita V. Adve,et al.  The impact of technology scaling on lifetime reliability , 2004, International Conference on Dependable Systems and Networks, 2004.

[18]  A.B. Kahng,et al.  Nontree routing for reliability and yield improvement [IC layout] , 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Yue Gao,et al.  Trading off area, yield and performance via hybrid redundancy in multi-core architectures , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[20]  Shantanu Gupta,et al.  Architectural core salvaging in a multi-core processor for hard-error tolerance , 2009, ISCA '09.

[21]  Chris C. N. Chu,et al.  DeFer: Deferred decision making enabled fixed-outline floorplanner , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[22]  C. Weber.  Yield learning and the sources of profitability in semiconductor manufacturing and process development , 2004, IEEE Transactions on Semiconductor Manufacturing.

[23]  Sandeep K. Gupta,et al.  Salvaging chips with caches beyond repair , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[24]  Doug Burger,et al.  Exploiting microarchitectural redundancy for defect tolerance , 2003, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[25]  Georges G. E. Gielen,et al.  Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies , 2008, 2008 Design, Automation and Test in Europe.