Modeling of Single-Event Upset in Bipolar Integrated Circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

[1]  R. Koga,et al.  Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs , 1982, IEEE Transactions on Nuclear Science.

[2]  T. R. Oldham,et al.  Charge Funneling in N- and P-Type Si Substrates , 1982, IEEE Transactions on Nuclear Science.

[3]  S. Kirkpatrick.  Modeling diffusion and collection of charge from ionizing radiation in silicon devices , 1979, IEEE Transactions on Electron Devices.

[4]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[5]  R. R. O'Brien,et al.  Collection of charge from alpha-particle tracks in silicon devices , 1983, IEEE Transactions on Electron Devices.

[6]  D. K. Nichols,et al.  Single Event Upset Sensitivity of Low Power Schottky Devices , 1982, IEEE Transactions on Nuclear Science.

[7]  J. B. Blake,et al.  Single Event Upset Vulnerability of Selected 4K and 16K CMOS Static RAM's , 1982, IEEE Transactions on Nuclear Science.

[8]  C. Hu,et al.  Alpha-particle-induced field and enhanced collection of carriers , 1982, IEEE Electron Device Letters.