Invited) How Far Can We Push Conventional Silicon Technology and What are the Future Alternatives

Silicon (Si) has dominated the microelectronics industry in the past. However, future Si technology is reaching practical and fundamental limits. To go beyond these limits novel devices like FinFETs, TunnelFETs, SpinFETs and higher mobility material like Ge and III-Vs are being aggressively studied to continue progress in integrated electronics. Recently Carbon nanotubes (CNT) and 2D materials like graphene, metal sulfides, telurides and selenides have emerged as potential candidates for nanoscale devices. The scaling paradigm is also threatened by interconnect limits including excessive power dissipation, insufficient bandwidth, and signal latency for both off-chip and on-chip applications. Many of these obstacles stem by the increase in Cu resistivity, as wire dimensions are reduced to nanoscale. This makes it imperative to examine alternate interconnect schemes for future such as CNTs, optical interconnects and 3-D integration. Is Ge PMOS and III-V NMOS co-integration on Si feasible or a headache for the manufacturing folks? Can CNT FETs become manufacturable? Are 2D materials more promising? Do the CNTs and graphene interconnects offer significant advantage over Cu/low-k? Will optical interconnects be ever integrated on a chip? This talk will try to answer some of these questions.