Compact and complete test set generation for multiple stuck-faults

We propose a novel procedure for testing all multiple stuck-faults in a logic circuit using two complementary algorithms. The first algorithm finds pairs of input vectors to detect the occurrence of target single stuck-faults independent of the occurrence of other faults. The second uses a sophisticated branch and bound procedure to complete the test set generation on the faults undetected by the first algorithm. The technique is complete and applies to all circuits. Experimental results presented in this paper demonstrate that compact and complete test sets can be quickly generated for standard benchmark circuits.

[1]  Journal of electronic testing: Theory and applications , 1995 .

[2]  Kozo Kinoshita,et al.  Test generation for multiple faults based on parallel vector pair analysis , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[3]  Eduard Cerny,et al.  On the generation of test patterns for multiple faults , 1993, J. Electron. Test..

[4]  The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need? , 1992, ITC.

[5]  Peter C. Maxwell,et al.  The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need? , 1992, ITC.

[6]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[7]  Kurt Keutzer,et al.  On properties of algebraic transformation and the multifault testability of multilevel logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Janusz Rajski,et al.  A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Joseph L. A. Hughes.  Multiple fault detection using single fault test sets , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Vinod K. Agarwal,et al.  Multiple Fault Testing of Large Circuits by Single Fault Test Sets , 1981, IEEE Transactions on Computers.

[11]  R. Dandapani,et al.  On the Design of Logic Networks with Redundancy and Testability Considerations , 1974, IEEE Transactions on Computers.

[12]  Sudhakar M. Reddy,et al.  Complete Test Sets for Logic Functions , 1973, IEEE Transactions on Computers.

[13]  Rodolfo Betancourt.  Derivation of Minimum Test Sets for Unate Logical Circuits , 1971, IEEE Transactions on Computers.