Improving the Detectability of Resistive Open Faults in Scan Cells
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[1] Camelia Hora,et al. Full Open Defects in Nanometric CMOS , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[2] Thomas M. Storey,et al. STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST , 1991, 1991, Proceedings. International Test Conference.
[3] Wayne M. Needham,et al. High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[4] C. Aissi,et al. Design and implementation of a fully testable CMOS D-latch , 1995, Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits.
[5] Samy Makar. Checking Experiments for Scan Chain Lathes and Flip-FLops , 1997 .
[6] Melvin A. Breuer,et al. A Universal Test Sequence for CMOS Scan , 1990 .
[7] Irith Pomeranz,et al. On the Detectability of Scan Chain Internal Faults An Industrial Case Study , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[8] Wojciech Maly,et al. CMOS bridging fault detection , 1990, Proceedings. International Test Conference 1990.
[9] Edward J. McCluskey,et al. Functional tests for scan chain latches , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[10] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[11] S.R. Makar,et al. Iddq test pattern generation for scan chain latches and flip-flops , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.
[12] Sudhakar Reddy,et al. Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops , 1986, IEEE Design & Test of Computers.
[13] Víctor H. Champac,et al. Testing of resistive opens in CMOS latches and flip-flops , 2005, European Test Symposium (ETS'05).
[14] F. Joel Ferguson,et al. Sandia National Labs , 2022 .
[15] Edward J. McCluskey,et al. Checking experiments to test latches , 1995, Proceedings 13th IEEE VLSI Test Symposium.
[16] R. L. Wadsack,et al. Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.
[17] Irith Pomeranz,et al. Detection of Internal Stuck-open Faults in Scan Chains , 2008, 2008 IEEE International Test Conference.
[18] Rosa Rodríguez-Montañés,et al. Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.
[19] Sandip Kundu,et al. On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits , 2008, 2008 Design, Automation and Test in Europe.
[20] Kevin Skadron,et al. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects , 2003 .
[21] Wu-Tung Cheng,et al. Detection and Diagnosis of Static Scan Cell Internal Defect , 2008, 2008 IEEE International Test Conference.
[22] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[23] Daniel Arumí,et al. Experimental Characterization of CMOS Interconnect Open Defects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[24] Víctor H. Champac,et al. Testability of floating gate defects in sequential circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.
[25] Edward J. McCluskey,et al. ATPG for scan chain latches and flip-flops , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[26] Rei-Fu Huang,et al. Testing Methodology of Embedded DRAMs , 2008, 2008 IEEE International Test Conference.