High-voltage circuits for power management on 65 nm CMOS

Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent. High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors. The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized. In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

[1]  Youngkook Ahn,et al.  5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity , 2012, IEEE Transactions on Power Electronics.

[2]  Dirk Killat,et al.  Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS , 2013, Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[3]  Maurits Ortmanns,et al.  An LDO using stacked transistors on 65 nm CMOS , 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

[4]  Maurits Ortmanns,et al.  Design of high speed high-voltage drivers based on stacked standard CMOS for various supply voltages , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[5]  Michael Fulde,et al.  A digitally controlled DC-DC converter for SoC in 28nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[6]  Michiel Steyaert,et al.  Design of High Voltage xDSL Line Drivers in Standard CMOS , 2008 .

[7]  Anantha Chandrakasan,et al.  20 $\mu$ A to 100 mA DC–DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[8]  Herbert L. Hess,et al.  An integrated high-voltage buck converter realized with a low-voltage cmos process , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[9]  Shanfeng Cheng,et al.  A fully integrated power-management solution for a 65nm CMOS cellular handset chip , 2011, 2011 IEEE International Solid-State Circuits Conference.