General analysis on the impact of phase-skew in time-interleaved ADCs
暂无分享,去创建一个
[1] Boris Murmann,et al. General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[2] Andreas Wiesbauer,et al. On the jitter requirements of the sampling clock for analog-to-digital converters , 2002 .
[3] Jean-François Naviner,et al. Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[4] A. Montijo,et al. A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[5] Rui Paulo Martins,et al. Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[6] Jieh-Tsorng Wu,et al. A background timing-skew calibration technique for time-interleaved analog-to-digital converters , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[7] W. Black,et al. Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[8] D. Draxelmayr,et al. A 6b 600MHz 10mW ADC array in digital 90nm CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[9] Christian Vogel,et al. The impact of combined channel mismatch effects in time-interleaved ADCs , 2005, IEEE Transactions on Instrumentation and Measurement.
[10] Bernard C. Levy,et al. Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] Kenneth W. Martin,et al. A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.
[12] Mark Horowitz,et al. A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.