Anomalous Stability Behavior of Synchronous Machine With High Impedance Faults

It is generally believed that following a fault, the system remains stable as long as the fault is cleared within a “critical clearing time” or CCT. This letter shows that when there is a high impedance resistive fault, there are later intervals such that if the fault is cleared within these intervals of time, the system is still stable notwithstanding that the clearing time is now larger than the conventionally calculated CCT. The results are obtained precisely using digital simulation and explained qualitatively using the equal area criterion.