Reconfigurable architecture for entropy decoding and inverse transform in H.264

Reconfigurable hardware is an effective design option for dealing with the increasing demands of flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods defined in the H.264 standard, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), using a coarse-grain reconfigurable architecture. An analyzing of the similarities and differences between these two decoding processes shows that CAVLC can be effectively merged into a CABAC decoder. Experimental results show that about 1.5K gates can be saved using the proposed reconfigurable cell (RC) architecture, which corresponds to a 25.4% area savings in the implementation of the CAVLC decoder. Using the idle time in RC arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences at Baseline and Main profiles at Level 3.0 under the real-time constraint.

[1]  Youn-Long Lin,et al.  A high-performance hardwired CABAC decoder for ultra-high resolution video , 2009, IEEE Transactions on Consumer Electronics.

[2]  Fabrizio S. Rovati,et al.  Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec , 2006, IEEE Transactions on Consumer Electronics.

[3]  Jiun-In Guo,et al.  A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing , 2006, 2006 IEEE International Conference on Multimedia and Expo.

[4]  Youn-Long Lin,et al.  A High-Performance Hardwired CABAC Decoder , 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

[5]  Jar-Ferr Yang,et al.  A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder , 2008, IEEE Transactions on Multimedia.

[6]  Jiun-In Guo,et al.  A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[7]  Wen Gao,et al.  Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Viktor K. Prasanna,et al.  Reconfigurable computing systems , 2002 .

[9]  Yong-Hwan Kim,et al.  Memory-efficient H.264/AVC CAVLC for fast decoding , 2006, IEEE Transactions on Consumer Electronics.

[10]  Yu Hen Hu,et al.  Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[11]  Wei Yu,et al.  A high performance CABAC decoding architecture , 2005, IEEE Transactions on Consumer Electronics.

[12]  Heiko Schwarz,et al.  Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[13]  Tian-Sheuan Chang,et al.  A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264 , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[14]  Jar-Ferr Yang,et al.  Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder , 2009, IEEE Transactions on Circuits and Systems for Video Technology.

[15]  I.-C. Park,et al.  High-Speed H.264/AVC CABAC Decoding , 2007, IEEE Transactions on Circuits and Systems for Video Technology.

[16]  Tsun-Han Tsai,et al.  An Efficient CAVLD Algorithm for H.264 Decoder , 2008, 2008 Digest of Technical Papers - International Conference on Consumer Electronics.

[17]  Martin Margala,et al.  A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[18]  Yong Ho Moon,et al.  An efficient decoding of CAVLC in H.264/AVC video coding standard , 2005, IEEE Transactions on Consumer Electronics.