Gate Sizing to Eliminate Crosstalk Induced Timing Violation

Digital circuits manufactured in deep sub-micron technologies may experience crosstalk-induced delay and noise signals. Crosstalk-induced delay can be quite significant and sensitive to the driver strength of coupling neighbors. In this paper, we propose gate-sizing techniques to reduce delay in presence of crosstalk effects. The techniques are based on our (2001) previously proposed crosstalk aware static timing analysis. Our experiments show that the proposed techniques are effective and may help designers achieve faster timing closure.

[1]  Malgorzata Marek-Sadowska,et al.  Worst Delay Estimation in Crosstalk Aware Static Timing Analysis , 2000, ICCD.

[2]  Malgorzata Marek-Sadowska,et al.  Functional correlation analysis in crosstalk induced critical paths identification , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[3]  Olivier Coudert,et al.  Gate sizing: a general purpose optimization approach , 1996, Proceedings ED&TC European Design and Test Conference.

[4]  Malgorzata Marek-Sadowska,et al.  Crosstalk Reduction by Transistor Sizing , 1999, ASP-DAC.

[5]  Malgorzata Marek-Sadowska,et al.  Crosstalk reduction for VLSI , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Tong Gao,et al.  Minimum Crosstalk Switchbox Routing , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[7]  Olivier Coudert,et al.  Gate sizing for constrained delay/power/area optimization , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Olivier Coudert,et al.  New algorithms for gate sizing: a comparative study , 1996, DAC '96.

[10]  Dongsheng Wang,et al.  Post global routing crosstalk risk estimation and reduction , 1996, ICCAD 1996.

[11]  Jason Cong,et al.  Global interconnect sizing and spacing with consideration of coupling capacitance , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[12]  Jason Cong,et al.  Interconnect sizing and spacing with consideration of couplingcapacitance , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Malgorzata Marek-Sadowska,et al.  Efficient Delay Calculation in Presence of Crosstalk , 2000, ISQED.

[14]  Malgorzata Marek-Sadowska,et al.  Efficient static timing analysis in presence of crosstalk , 2000 .