Real-Time Synthesis is Hard!
暂无分享,去创建一个
Benjamin Monmege | Nathalie Sznajder | Thomas Brihaye | Gilles Geeraerts | Hsi-Ming Ho | Morgane Estiévenart | G. Geeraerts | N. Sznajder | B. Monmege | Morgane Estiévenart | Hsi-Ming Ho | Thomas Brihaye
[1] Joël Ouaknine,et al. Universality and Language Inclusion for Open and Closed Timed Automata , 2003, HSCC.
[2] Kim G. Larsen,et al. Efficient On-the-Fly Algorithms for the Analysis of Timed Games , 2005, CONCUR.
[3] Pierre-Yves Schobbens,et al. Fully decidable logics, automata and classical theories for defining regular real-time languages , 1999 .
[4] Thomas A. Henzinger,et al. The Element of Surprise in Timed Games , 2003, CONCUR.
[5] Joël Ouaknine,et al. Safety Metric Temporal Logic Is Fully Decidable , 2006, TACAS.
[6] Thomas A. Henzinger,et al. The benefits of relaxing punctuality , 1991, PODC '91.
[7] Ron Koymans,et al. Specifying real-time properties with metric temporal logic , 1990, Real-Time Systems.
[8] Joël Ouaknine,et al. The Cost of Punctuality , 2007, 22nd Annual IEEE Symposium on Logic in Computer Science (LICS 2007).
[9] P. Madhusudan,et al. Timed Control Synthesis for External Specifications , 2002, STACS.
[10] Morgane Estiévenart. Verification and synthesis of MITL through alternating timed automata , 2015 .
[11] Joël Ouaknine,et al. On the decidability and complexity of Metric Temporal Logic over finite words , 2007, Log. Methods Comput. Sci..
[12] Kim G. Larsen,et al. Efficient controller synthesis for a fragment of $$\hbox {MTL}_{0, \infty }$$MTL0,∞ , 2013, Acta Informatica.
[13] Daniel Brand,et al. On Communicating Finite-State Machines , 1983, JACM.
[14] Jean-François Raskin,et al. An Antichain Algorithm for LTL Realizability , 2009, CAV.
[15] Thomas Brihaye,et al. On MITL and Alternating Timed Automata , 2013, FORMATS.
[16] Krishnendu Chatterjee,et al. Algorithms for Omega-Regular Games with Imperfect Information , 2006, Log. Methods Comput. Sci..
[17] Patricia Bouyer,et al. Controller Synthesis for MTL Specifications , 2006, CONCUR.
[18] Rajeev Alur,et al. A Theory of Timed Automata , 1994, Theor. Comput. Sci..
[19] Véronique Bruyère,et al. Acacia+, a Tool for LTL Synthesis , 2012, CAV.
[20] A. Pnueli,et al. On the Synthesis of an Asynchronous Reactive Module , 1989, ICALP.
[21] KoymansRon. Specifying real-time properties with metric temporal logic , 1990 .
[22] Jean-François Raskin,et al. Realizability of Real-Time Logics , 2009, FORMATS.