NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.

[1]  D.R. Bearden,et al.  A 780 MHz PowerPC/sup TM/ microprocessor with integrated L2 cache , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  Y. Berg,et al.  Robust low-power CMOS precharge logic , 2013, 2013 IEEE Faible Tension Faible Consommation.

[3]  Rajesh Kumar,et al.  Interconnect and noise immunity design for the Pentium 4 processor , 2003, DAC.

[4]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[5]  Duncan G. Elliott,et al.  Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Tadashi Shibata,et al.  Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[7]  John P. Uyemura Introduction to CMOS , 1992 .

[8]  Y. Berg Novel high speed differential CMOS flip-flop for ultra low-voltage appications , 2011, 2011 IEEE 9th International New Circuits and systems conference.

[9]  Y. Berg,et al.  Ultra low-voltage and high speed dynamic and static CMOS precharge logic , 2012, 2012 IEEE Faible Tension Faible Consommation.

[10]  E. You,et al.  A third-generation SPARC V9 64-b microprocessor , 2000, IEEE Journal of Solid-State Circuits.

[11]  Omid Mirmotahari,et al.  High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates , 2012 .

[12]  Yngvar Berg,et al.  Ultra low-voltage/low-power digital floating-gate circuits , 1999 .

[13]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[14]  O. Takahashi,et al.  A 1.0 GHz single-issue 64 b powerPC integer processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[15]  Tor Sverre Lande,et al.  Programming floating-gate circuits with UV-activated conductances , 2001 .

[16]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .