Testing power-delivery TSVs

Many TSVs in a 3D IC are not used for signal transmission but for power delivery. Techniques needed to detect them have not been studied in-depth in the literature. In this paper, we present a test method for power-delivery TSVs, by embedding ring-oscillator (RO) based monitors (in a scalable architecture) to detect if there is any excessive voltage-drop at the end of any TSV during a manufacturing test session. One key feature as opposed to previous RO-based methods is that our approach is able to detect the worst-case dynamic voltage-drop (occurring in a very short period of time such as 1ns), rather than just the average voltage-drop over a long period of time. This is essential in order to detect small defects inside the power delivery network. These defects, if not detected, could set off a transient timing failure when the IC is operated in a system.

[1]  Fangming Ye,et al.  TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.

[2]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[3]  T. Rahal-Arabi,et al.  On-die droop detector for analog sensing of power supply noise , 2004, IEEE Journal of Solid-State Circuits.

[4]  Ding-Ming Kwai,et al.  A built-in self-test scheme for the post-bond test of TSVs in 3D ICs , 2011, 29th VLSI Test Symposium.

[5]  P. Andry,et al.  Characterization of micro-bump C4 interconnects for Si-carrier SOP applications , 2006, 56th Electronic Components and Technology Conference 2006.

[6]  Alfred L. Crouch,et al.  Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip , 2007, 2007 IEEE International Test Conference.

[7]  Yukiya Miura,et al.  Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test , 2014, 2014 IEEE 23rd Asian Test Symposium.

[8]  Alfred L. Crouch,et al.  Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks , 2006, 2006 IEEE International Test Conference.

[9]  S. L. Wright,et al.  Micro-interconnection reliability: Thermal, electrical and mechanical stress , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[10]  Shi-Yu Huang,et al.  Pulse-Vanishing Test for Interposers Wires in 2.5-D IC , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Doug Josephson,et al.  Voltage transient detection and induction for debug and test , 2009, 2009 International Test Conference.

[12]  Shi-Yu Huang,et al.  Worst-case IR-drop monitoring with 1GHz sampling rate , 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

[13]  Shi-Yu Huang,et al.  Small delay testing for TSVs in 3-D ICs , 2012, DAC Design Automation Conference 2012.

[14]  Shi-Yu Huang,et al.  Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[16]  K.A. Jenkins,et al.  On-chip Real-Time Power Supply Noise Detector , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.