High-speed hardware efficient FIR compensation filter for Delta-Sigma modulator analog-to-digital converter in 0.13 µm CMOS technology

A high-speed hardware efficient 41-tap, 15-bit word length Finite Impulse Response (FIR) Compensation Filter has been designed as a component in a Delta-Sigma Modulator (DSM) Analog-to-Digital Converter (ADC). The filter is targeted for high-throughput by pipelining its adders and multipliers. Efficient circuit-level techniques, namely customized adders, multipliers and D-flip-flop (DFF) are used to further improve performance. The FIR filter is implemented in CMOS 0.13 µm technology which contains approximately 180K transistors and occupies 2.69 mm2 area. The filter is capable of operating at a maximum clock rate of 1.25 GHz.