Gemini NI: An Integration of Two Network Interfaces

According to the development of the TOP500, the performance of the high performance computers (HPCs) is increasing rapidly. The incredible performance increment of the HPCs should be largely attributed to the development of their communication systems, because the HPCs cannot extend to such a large scale without their excellent communication systems. As an important member of the communication system, the network interface (NI) always plays a significant role. Since the network interface locates on the critical path of the communication system, it can easily become a bottleneck if it cannot provide low latency and high bandwidth for communication. The Gemini NI presented in this paper has a good performance potential in both latency and bandwidth. It has a remote load/store (RLS) mechanism which can provide ultra low latency. Furthermore, it has two HyperTransport (HT) interfaces connected to double processors or symmetric multi-processors (SMP), and it has four proprietary switch interfaces connected to the switches. This approach largely in-creases the throughput of the Gemini NI. Inside the Gemini NI, almost all the components of a network interface are duplicated. The resource sharing within the Gemini NI can provide great flexibility for scheduling. A FPGA prototype of the Gemini NI has been implemented, and the preliminary results prove the validity of our design.

[1]  Zheng Cao,et al.  Design of Barrier Network of Dawning 5000 High Performance Computer: Design of Barrier Network of Dawning 5000 High Performance Computer , 2009 .

[2]  Kai Li,et al.  HPP: An Architecture for High Performance and Utility Computing: HPP: An Architecture for High Performance and Utility Computing , 2009 .

[3]  Henri E. Bal,et al.  User-Level Network Interface Protocols , 1998, Computer.

[4]  Jie Ma,et al.  HPPNET: A novel network for HPC and its implication for communication software , 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

[5]  K. K. Ramakrishnan,et al.  Performance Considerations in Designing Network Interfaces , 1993, IEEE J. Sel. Areas Commun..

[6]  Keith D. Underwood,et al.  SeaStar Interconnect: Balanced Bandwidth for Scalable Performance , 2006, IEEE Micro.

[7]  Wei Huang,et al.  Performance Analysis and Evaluation of PCIe 2.0 and Quad-Data Rate InfiniBand , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[8]  Evangelos P. Markatos,et al.  User-level DMA without operating system kernel modification , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

[9]  Keith D. Underwood,et al.  Initial performance evaluation of the Cray SeaStar interconnect , 2005, 13th Symposium on High Performance Interconnects (HOTI'05).

[10]  Cao Zheng Design of Barrier Network of Dawning 5000 High Performance Computer , 2008 .

[11]  Keith D. Underwood,et al.  A preliminary analysis of the InfiniPath and XD1 network interfaces , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

[12]  Dave Olson,et al.  Pathscale InfiniPath: a first look , 2005, 13th Symposium on High Performance Interconnects (HOTI'05).

[13]  Ninghui Sun HPP: an architecture for high performance and utility computing , 2007, China HPC.

[14]  Dawei Wang,et al.  HPP Switch: A Novel High Performance Switch for HPC , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[15]  Andrew A. Chien,et al.  Design Challenges for High-Performance Network Interfaces - Guest Editors' Introduction , 1998, Computer.