Design of a Nanometric Reversible 4-Bit Binary Counter with Parallel Load

In recent years, reversible logic has considered as an efficient computing method having its applications in quantum computing, low power computing, nanotechnology and DNA computing. All of the Boolean functions can be implemented using reversible gates. In this paper, we propose a reversible 4-Bit binary counter with parallel load. It has minimum complexity and quantum cost considerably. The proposed circuit is the first attempt of designing a 4-Bit binary counter with parallel load. Counter is essentially a register that goes through a predetermined sequence of states. The reversible gates in the counter are connected in such a way as to produce the prescribed sequence of binary states. This counter receives a 4-Bit data from input and delivers data to D Flip Flop in next cycle. Loading data from input is determined with Load property. The important reversible gates used for our reversible logic synthesis are Feynman gate, Peres gate and Fredkin gate. The proposed circuit becomes a robust design by our optimal method and using these gates. The proposed circuit has minimum number of the garbage outputs and constant inputs in reversible circuit. The proposed circuit is the first attempt and efficient state for a nanometric reversible 4-Bit binary counter. More complex systems could be constructed using the proposed circuit.

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