A 2-GHz low-power single-chip CMOS receiver for WCDMA applications

This paper describes a 2-GHz single-chip 0.25-µm CMOS receiver for WCDMA applications. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s ΣΔ analog-to-digital converter operating at 200 MHz. The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW.

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