/spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC

A continuous-time 1 b /spl Sigma//spl Delta/ ADC with a finite impulse response DAC in the feedback path is presented. The FIRDAC reduces the susceptibility to clock jitter by 18 dB while maintaining linearity. S/N ratio is 77 dB in a 1 MHz bandwidth, and IM2 and IM3 are 77 dB and 82 dB, respectively. The 0.18 /spl mu/m CMOS chip consumes 6.0 mW.

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