High-speed dynamic partial reconfiguration for field programmable gate arrays
暂无分享,去创建一个
[1] Philip James-Roxby,et al. A Self-reconfiguring Platform , 2003, FPL.
[2] W. Shedd,et al. Dose Rate Upset Investigations on the Xilinx Virtex IV Field Programmable Gate Arrays , 2007, 2007 IEEE Radiation Effects Data Workshop.
[3] Clive ldMax rd Maxfield,et al. The design warrior's guide to FPGAs , 2004 .
[4] Kris Gaj,et al. Secure partial reconfiguration of FPGAs , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..
[5] Jürgen Becker,et al. Dynamic and Partial FPGA Exploitation , 2007, Proceedings of the IEEE.
[6] Bin Zhang,et al. A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[7] Brad L. Hutchings,et al. A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[8] Guillermo A. Vera. A dynamic arithmetic architecture: precision, power and performance considerations , 2008 .
[9] Patrick Lysaght,et al. Self Controlling Dynamic Reconfiguration: A Case Study , 1999, FPL.
[10] Uwe Meyer-Baese,et al. An FPGA-based rapid prototyping platform for wavelet coprocessors , 2007, SPIE Defense + Commercial Sensing.
[11] Neil W. Bergmann,et al. Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-on-Chip , 2004, ERSA.
[12] Marios S. Pattichis,et al. Integrating Reconfigurable Logic in the First Digit al Logic Course , 2006 .
[13] Uwe Meyer-Baese,et al. Discrete wavelet transform FPGA design using MatLab/Simulink , 2006, SPIE Defense + Commercial Sensing.
[14] Scott McMillan,et al. A lightweight approach for embedded reconfiguration of FPGAs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.