Low-Power High-Resolution 32-channel Neural Recording System

A design of low-power 32-channel neural recording system with on-chip high-resolution A/D converters is presented. A neural front-end including low-noise fully differential pre-amplifier, gain stage, and buffer consumes only 56 muW. Two 13-bits extended counting A/D converters running at 512 KHz sampling rate are integrated with 32 neural front-ends on a chip. The experimental prototype was designed in 0.6 mum CMOS process. With a 3.3 V power supply, total power consumption of a chip is 22 mW and the whole system occupies an area of 3 mm times 3 mm.

[1]  R. R. Harrison,et al.  A low-power low-noise CMOS amplifier for neural recording applications , 2003, IEEE J. Solid State Circuits.

[2]  K. Wise,et al.  An implantable multielectrode array with on-chip signal processing , 1986 .

[3]  M. Waltari,et al.  A 10-bit 200 MS/s CMOS parallel pipeline A/D converter , 2001, Proceedings of the 26th European Solid-State Circuits Conference.

[4]  Pieter Rombouts,et al.  A 13.5-b 1.2-V micropower extended counting A/D converter , 2001, IEEE J. Solid State Circuits.

[5]  Ran Ginosar,et al.  An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection , 2007, IEEE Trans. Biomed. Eng..

[6]  R. R. Harrison,et al.  A floating gate common mode feedback circuit for low noise amplifiers , 2003, Southwest Symposium on Mixed-Signal Design, 2003..

[7]  R.R. Harrison,et al.  A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System , 2006, IEEE Journal of Solid-State Circuits.

[8]  Khalil Najafi,et al.  A new dc baseline stabilization scheme for neural recording microprobes , 1999, Proceedings of the First Joint BMES/EMBS Conference. 1999 IEEE Engineering in Medicine and Biology 21st Annual Conference and the 1999 Annual Fall Meeting of the Biomedical Engineering Society (Cat. N.