Three-dimensional packaging for multi-chip module with through-the-silicon via hole

This paper presents an innovative package design for multi-chip modules. The developed package has a flip-chip-on-chip structure. Four memory chips (DRAM for demonstration) are assembled on a silicon chip carrier with eutectic Sn-Pb solder joints. The I/Os of memory chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. An optional through-the-silicon via hole is made at the center of the chip carrier for underfill dispensing, if required. The whole multi-chip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly, all specimens are inspected by X-ray and divided into two groups. One group is encapsulated with underfill and the other group is not. For those packages with encapsulation, the underfill is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. Subsequently, scanning acoustic microscopy is performed to inspect the quality of underfill. Afterwards, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of those packages is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1,000 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, right under the pads of large solder balls. The ATC test of packages with underfill encapsulation is still ongoing (no observable failure recorded up to 1,200 cycles). With this innovative package design, low profile and high density multi-chip modules can be implemented. Due to the unique package structure and underfill encapsulation, it is believed that good board level reliability can be achieved.

[1]  Kaustav Banerjee,et al.  Performance analysis and technology of 3-D ICs , 2000, SLIP '00.

[2]  A. Youngblood,et al.  Challenges in packaging a 4 chip FC MCM-L using KGD , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

[3]  M. Tomisaka,et al.  Thermal characterization of bare-die stacked modules with Cu through-vias , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[4]  R. Reif,et al.  Thermal analysis of three-dimensional (3-D) integrated circuits (ICs) , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[5]  K. Warner,et al.  Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[6]  K. Saraswat,et al.  Controlled two-step solid-phase crystallization for high-performance polysilicon TFT's , 1997, IEEE Electron Device Letters.

[7]  Kaustav Banerjee,et al.  Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnects , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[8]  C. Beddingfield,et al.  Flip chip assembly of Motorola fast static RAM known good die , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.

[9]  Rao Tummala,et al.  Fundamentals of Microsystems Packaging , 2001 .

[10]  Anna W. Topol,et al.  Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication , 2002, Digest. International Electron Devices Meeting,.

[11]  A. Fan,et al.  Copper Wafer Bonding , 1999 .

[12]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[13]  D. Robinson,et al.  Motorola fast static RAM known good die manufacturing process , 1997, Proceedings 1997 International Conference on Multichip Modules.

[14]  Sung-Mo Kang,et al.  Cell-level placement for improving substrate thermal distribution , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  R. S. Li.  Optimization of thermal via design parameters based on an analytical thermal resistance model , 1998, ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208).

[16]  M. Michael Yovanovich,et al.  Analysis of thermal vias in high density interconnect technology , 1992, [1992 Proceedings] Eighth Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[17]  Sangwoo Pae,et al.  Multiple layers of silicon-on-insulator for nanostructure devices , 1999 .

[18]  J. Lau,et al.  Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies , 1996 .

[19]  Kavagi Levis,et al.  Assembly and solder joint reliability of plastic ball grid array with lead-free versus lead-tin interconnect , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[20]  Sachin S. Sapatnekar,et al.  Thermal via placement in 3D ICs , 2005, ISPD '05.

[21]  M. Morimoto,et al.  Three dimensional ICs, having four stacked active device layers , 1989, International Technical Digest on Electron Devices Meeting.

[22]  M.T.W. de Langen.  Low Cost Flip Chip Technology , 1997 .

[23]  A.Y. Zeng,et al.  Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs , 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

[24]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[25]  Le Luo,et al.  Multi-chip memory module vvith a flip-chip-on-chip structure and an optional center via hole for underfill dispensing , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[26]  J.W. Joyner,et al.  A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[27]  A. Youngblood,et al.  Flip chip MCM-L using known good die , 1998, Proceedings. 1998 International Conference on Multichip Modules and High Density Packaging (Cat. No.98EX154).

[28]  Yangdong Deng,et al.  2.5D system integration: a design driven system implementation schema , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[29]  Nisha Checka,et al.  Technology, performance, and computer-aided design of three-dimensional integrated circuits , 2004, ISPD '04.

[30]  Anantha Chandrakasan,et al.  Three-dimensional integrated circuits: performance, design methodology, and CAD tools , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[31]  M. Turowski,et al.  Fast, automated thermal simulation of three-dimensional integrated circuits , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).

[32]  Krishna C. Saraswat,et al.  High-performance germanium-seeded laterally crystallized TFTs for vertical device integration , 1998 .

[33]  C. Keast,et al.  An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[34]  K. Saraswat,et al.  Analytical thermal model for multilevel VLSI interconnects incorporating via effect , 2002, IEEE Electron Device Letters.

[35]  M. K. Iyer,et al.  Thermal characterization of vias using compact models , 2000, Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456).

[36]  K.C. Saraswat,et al.  Thermal analysis of heterogeneous 3D ICs with various integration scenarios , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[37]  Kaustav Banerjee,et al.  Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[38]  S. Das,et al.  Fabrication technologies for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.

[39]  A. Rahman,et al.  Comparison of key performance metrics in two- and three-dimensional integrated circuits , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).