A Flexible NISC-Based LDPC Decoder
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[1] Hans-Jörg Pfleiderer,et al. FPGA implementation of a flexible decoder for long LDPC codes , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[2] D.E. Hocevar,et al. A reduced complexity decoder architecture via layered decoding of LDPC codes , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..
[3] Jianming Cui,et al. An multi-rate LDPC decoder based on ASIP for DMB-TH , 2009, 2009 IEEE 8th International Conference on ASIC.
[4] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[5] David J. C. MacKay,et al. Good Error-Correcting Codes Based on Very Sparse Matrices , 1997, IEEE Trans. Inf. Theory.
[6] Zhiyi Yu,et al. A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost , 2012, 2012 IEEE International Symposium on Circuits and Systems.
[7] Bertrand Le Gal,et al. Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards , 2012, 2012 IEEE Workshop on Signal Processing Systems.
[8] Robert Michael Tanner,et al. A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.
[9] A. Bourdoux,et al. A flexible ASIP decoder for combined binary and non-binary LDPC codes , 2010, 2010 17th IEEE Symposium on Communications and Vehicular Technology in the Benelux (SCVT2010).
[10] Bormin Huang,et al. Accelerating Regular LDPC Code Decoders on GPUs , 2011, IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing.
[11] Leonel Sousa,et al. Massively LDPC Decoding on Multicore Architectures , 2011, IEEE Transactions on Parallel and Distributed Systems.
[12] Cyrille Chavet,et al. A memory mapping approach for parallel interleaver design with multiples read and write accesses , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[13] Liesbet Van der Perre,et al. A unified instruction set programmable architecture for multi-standard advanced forward error correction , 2008, 2008 IEEE Workshop on Signal Processing Systems.
[14] Brendan J. Frey,et al. Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.
[15] Jean-Luc Danger,et al. Generic Description and Synthesis of LDPC Decoders , 2007, IEEE Transactions on Communications.
[16] Catherine Douillard,et al. Design and FPGA prototyping of a bit-interleaved coded modulation receiver for the DVB-T2 standard , 2010, 2010 IEEE Workshop On Signal Processing Systems.
[17] V. Benes,et al. Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .
[18] Guido Masera,et al. ASIP design for partially structured LDPC codes , 2006 .
[19] N. Wehn,et al. FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding , 2008, 2008 5th International Symposium on Turbo Codes and Related Topics.
[20] Joseph R. Cavallaro,et al. GPU accelerated scalable parallel decoding of LDPC codes , 2011, 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR).
[21] Sae-Young Chung,et al. On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit , 2001, IEEE Communications Letters.
[22] Joseph R. Cavallaro,et al. Unified decoder architecture for LDPC/turbo codes , 2008, 2008 IEEE Workshop on Signal Processing Systems.
[23] Amer Baghdadi,et al. A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding , 2011, 2011 Design, Automation & Test in Europe.
[24] Frank Kienle,et al. A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding , 2006, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications.
[25] Guido Masera,et al. VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[26] Luca Fanucci,et al. A multi-standard flexible turbo/LDPC decoder via ASIC design , 2010, 2010 6th International Symposium on Turbo Codes & Iterative Information Processing.
[27] Jinghu Chen,et al. Density evolution for two improved BP-Based decoding algorithms of LDPC codes , 2002, IEEE Communications Letters.
[28] Sergio Benedetto,et al. Mapping interleaving laws to parallel turbo and LDPC decoder architectures , 2004, IEEE Transactions on Information Theory.
[29] Gerhard Fettweis,et al. ASIP decoder architecture for convolutional and LDPC codes , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[30] Guido Masera,et al. Implementation of a Flexible LDPC Decoder , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.
[31] Leonel Sousa,et al. GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection , 2011 .
[32] Daniel Gajski,et al. A cycle-accurate compilation algorithm for custom pipelined datapaths , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).