Lightweight hierarchical error control codes for multi-bit differential channels
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[1] Jien-Chung Lo. A Hyper Optimal Encoding Scheme for Self-Checking Circuits , 1996, IEEE Trans. Computers.
[2] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[3] Elwyn R. Berlekamp,et al. Algebraic coding theory , 1984, McGraw-Hill series in systems science.
[4] James L. Massey,et al. Shift-register synthesis and BCH decoding , 1969, IEEE Trans. Inf. Theory.
[5] Torleiv Kløve,et al. The undetected error probability threshold of m-out-of-n codes , 2000, IEEE Trans. Inf. Theory.
[6] Donald M. Chiarulli,et al. Area, power, and pin efficient bus transceiver using multi-bit-differential signaling , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[7] S. K. Leung-Yan-Cheong,et al. Concerning a Bound on Undetected Error Probability , 1970 .
[8] B.W. Langley,et al. Superconducting interconnects for VLSI multi-chip system integration , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.
[9] R. Vounckx,et al. A power reduction method for off-chip interconnects , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).
[10] H. Melchior,et al. Demonstration of 2-D plastic optical fibre based optical interconnect between CMOS ICs , 2001, OFC 2001. Optical Fiber Communication Conference and Exhibit. Technical Digest Postconference Edition (IEEE Cat. 01CH37171).
[11] David A. Johns,et al. Power efficient chip-to-chip signaling schemes , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[12] J. Macwilliams. A theorem on the distribution of weights in a systematic code , 1963 .
[13] R. Dennard,et al. Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance , 1992 .
[14] C. E. SHANNON,et al. A mathematical theory of communication , 1948, MOCO.
[15] George Varghese,et al. Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[16] Y Li,et al. Fiber-image-guide-based bit-parallel optical interconnects. , 1996, Applied optics.
[17] B. Young. An SOI CMOS LVDS driver and receiver pair , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[18] Alister G. Burr. Turbo-codes: the ultimate error control codes? , 2001 .
[19] Paul D. Franzon,et al. 4 Gbps high-density AC coupled interconnection , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
[20] James L. Massey,et al. Step-by-step decoding of the Bose-Chaudhuri- Hocquenghem codes , 1965, IEEE Trans. Inf. Theory.
[21] Yixian Yang,et al. On the undetected error probability of nonlinear binary constant weight codes , 1994, IEEE Trans. Commun..
[22] John Teifel,et al. A high-speed clockless serial link transceiver , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..
[23] Donald M. Chiarulli,et al. Active substrates for optoelectronic interconnect , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[24] Mark Horowitz,et al. High-speed electrical signaling: overview and limitations , 1998, IEEE Micro.
[25] Donald M. Chiarulli,et al. System-level modeling and Simulation of the 10G optoelectronic interconnect , 2003 .
[26] F. Lemmermeyer. Error-correcting Codes , 2005 .
[27] R. Engelbrecht,et al. DIGEST of TECHNICAL PAPERS , 1959 .
[28] C. B. Shung,et al. A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications , 1998 .
[29] Matthew N. O. Sadiku,et al. Elements of Electromagnetics , 1989 .
[30] Richard W. Hamming,et al. Error detecting and error correcting codes , 1950 .
[31] Hanho Lee. High-speed VLSI architecture for parallel Reed-Solomon decoder , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[32] F. MacWilliams,et al. The Theory of Error-Correcting Codes , 1977 .
[33] M. Horowitz,et al. A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation , 2000, IEEE Journal of Solid-State Circuits.
[34] A. Bogliolo,et al. Encodings for high-performance energy-efficient signaling , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).
[35] Mircea R. Stan,et al. Low-power encodings for global communication in CMOS VLSI , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[36] Herbert O. Burton. Inversionless decoding of binary BCH codes , 1971, IEEE Trans. Inf. Theory.
[37] Daniel A. Spielman,et al. Efficient erasure correcting codes , 2001, IEEE Trans. Inf. Theory.
[38] Donald M. Chiarulli,et al. Area-, power-, and pin-efficient bus structures using multi-bit-differential signaling , 2005, SPIE Microtechnologies.
[39] W. W. Peterson,et al. Encoding and error-correction procedures for the Bose-Chaudhuri codes , 1960, IRE Trans. Inf. Theory.
[40] Elwyn R. Berlekamp,et al. On decoding binary Bose-Chadhuri- Hocquenghem codes , 1965, IEEE Trans. Inf. Theory.
[41] Cheng-Wen Wu,et al. Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code , 1999, IEEE Trans. Computers.
[42] Ron M. Roth,et al. Location-correcting codes , 1996, IEEE Trans. Inf. Theory.
[43] John Poulton. Problems and prospects for electrical signaling [VLSI] , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.
[44] Nicholas Cravotta. RapidIOversus HyperTransport : A battle between equals or unintentional marketing confusion ? , 2002 .
[46] M W Haney,et al. Multichip free-space global optical interconnection demonstration with integrated arrays of vertical-cavity surface-emitting lasers and photodetectors. , 1999, Applied optics.
[47] Xia Fang,et al. A new VLSI design for decoding of Reed-Solomon codes based on ASIP [HDTV] , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).
[48] D V Plant,et al. Interconnection of a two-dimensional array of vertical-cavity surface-emitting lasers to a receiver array by means of a fiber image guide. , 2000, Applied optics.
[49] Ted H. Szymanski. Optical link optimization using embedded forward error correcting codes , 2003 .
[50] Claude E. Shannon,et al. A Mathematical Theory of Communications , 1948 .
[51] W. W. Peterson,et al. Error-Correcting Codes. , 1962 .
[52] Dwijendra K. Ray-Chaudhuri,et al. Binary mixture flow with free energy lattice Boltzmann methods , 2022, arXiv.org.
[53] H. Tamura,et al. PRD-based global-mean-time signaling for high-speed chip-to-chip communications , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[54] Stefan Hirsch,et al. CMOS receiver circuits for high-speed data transmission according to LVDS-standard , 2003, SPIE Microtechnologies.
[55] S C Esener,et al. Free-space parallel multichip interconnection system. , 2000, Applied optics.
[56] Tenkasi V. Ramabadran,et al. A coding scheme for m-out-of-n codes , 1990, IEEE Trans. Commun..
[57] Mark Horowitz,et al. A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation , 2000 .
[58] Donald M. Chiarulli,et al. Optoelectronic Multi-Chip Module Demonstration System , 2003 .
[59] Magdy S. Abadir,et al. Minimal test for coupling faults in word-oriented memories , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[60] Donald M. Chiarulli,et al. Optoelectronic Multi-Chip-Module Implementation of a 64-Channel Fiber Switch , 2001 .
[61] W. Wilhelm. A new scalable VLSI architecture for Reed-Solomon decoders , 1999 .
[62] Ron M. Roth,et al. On MDS extensions of generalized Reed-Solomon codes , 1986, IEEE Trans. Inf. Theory.
[63] Toby Berger,et al. Coding for noisy channels with input-dependent insertions , 1977, IEEE Trans. Inf. Theory.
[64] Y Li,et al. Polymer fiber-image-guide-based embedded optical circuit board. , 1999, Applied optics.
[65] Shu Lin,et al. Error control coding : fundamentals and applications , 1983 .
[66] Mark Horowitz,et al. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers , 1997 .
[67] Robert McEliece,et al. The Theory of Information and Coding: Information theory , 2002 .
[68] Wolfgang Willems,et al. Codes of Small Defect , 1997, Des. Codes Cryptogr..
[69] T. Lee,et al. A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter , 1999 .
[70] D. C. Hiarulli,et al. OPTOELECTRONIC MULTI-CHIP MODULES , 2004 .
[71] Kurt Keutzer,et al. Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express , 2004 .
[72] Jah-Ming Hsu,et al. An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm , 1997, IEEE Trans. Circuits Syst. Video Technol..
[73] G. David Forney,et al. On decoding BCH codes , 1965, IEEE Trans. Inf. Theory.
[74] Tadao Kasami. A decoding procedure for multiple-error-correcting cyclic codes , 1964, IEEE Trans. Inf. Theory.
[75] Donatella Sciuto,et al. Conditions for the design of circuits with concurrent error detection properties , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[76] Hyunchul Shin,et al. An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs , 1997 .
[77] L. Benini,et al. Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.
[78] Kiyoung Choi,et al. Narrow bus encoding for low-power DSP systems , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[79] H. Blennemann,et al. Off-chip 400 Mbps signal transmission: noise reduction using non-resonant lengths and other techniques , 1996, Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893).
[80] Hsie-Chia Chang,et al. A low-power Reed-Solomon decoder for STM-16 optical communications , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.
[81] Van Nostrand,et al. Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm , 1967 .