Maximum projections of don't care conditions in a Boolean network

The maximum flexibility of a function at a node in a Boolean network is described by the incompletely specified function formed using the union of the satisfiability don't-care set (SDC) and observability don't-care set (ODC) of the node. The normal representation of these sets depends on every variable in the network, can be quite large and may be hard to compute. Usually, we are only interested in the don't care set when restricted to a certain set of variables. We give a formulation for the don't care set of a node in terms of a pre-specified set of variables and prove that this formulation is the maximum projection of the entire don't care set onto the chosen set of variables. This formulation allows computation to start at the target node and proceed by traversing the network outwards. The computation may be stopped at any time yielding a valid subset of the don't care set.

[1]  Robert K. Brayton,et al.  Multilevel logic synthesis , 1990, Proc. IEEE.

[2]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[3]  Robert K. Brayton,et al.  Extracting local don't cares for network optimization , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[4]  Eduard Cerny,et al.  An Approach to Unified Methodology of Combinational Switching Circuits , 1977, IEEE Transactions on Computers.

[5]  Giovanni De Micheli,et al.  Observability don't care sets and Boolean relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[6]  Carl Sechen,et al.  Boolean division and factorization using binary decision diagrams , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Robert K. Brayton,et al.  Multi-Level Logic Simplification Using Don't Cares and Filters , 1989, 26th ACM/IEEE Design Automation Conference.

[9]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.