A lower error antilogarithmic converter using novel four-region piecewise-linear approximation

In this paper, a novel antilogarithmic converter using four-region piecewise-linear approximation is proposed. The proposed technique provides a lower error and area-efficient hardware implementation for antilogarithmic converter with 0.5681% of percent error range, which can outperform previously proposed methods with four-region and six-region schemes. The delay and area of the hardware implementation is 10ns and 6,639 μm2, respectively using 0.18 μm TSMC process.