Semiconductor memory devices

It provides a semiconductor memory device of the twin-cell method. The memory device includes a main bit line region and the reference bit line areas. The main bit line region is arranged with a plurality of main bit lines which are parallel to each other along the rows (columns), the reference bit line region of a plurality of parallel to the main bit lines, each corresponding to the main bit line in parallel to a reference bit line it is disposed. It said main bit line and said reference bit line, the plurality of sense amplifiers are electrically connected to each other. Wherein each of said sense amplifiers is the between the main bit lines one and its equivalent the reference bit line is electrically connected to, said main bit line and the reference bit line connected to each of the sense amplifier that of at least one interposed among the main bit line and the reference bit line.