Digital circuit design for minimum transient energy and a linear programming method

This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum difference between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay buffers. The minimum transient energy design is obtained when no delay buffer is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay buffers may have to be added. The theory in this paper allows trade-offs between minimum transient energy and critical path delay. We formulate the problem as a linear program to obtain the minimum transient energy design with the smallest number of delay buffers for a given overall delay of the circuit. An optimized four-bit ALU circuit is found to consume 53% peak and 73% average power compared to the original circuit.