On the Evolution of Hardware Circuits via Reconfigurable Architectures

Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed---the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature. FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over Reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

[1]  Ronald F. DeMara,et al.  Layered Approach to Intrinsic Evolvable Hardware using Direct Bitstream Manipulation of Virtex II Pro Devices , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[2]  E. Stomeo,et al.  Generalized Disjunction Decomposition for Evolvable Hardware , 2006, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[3]  Paul J. Layzell,et al.  Explorations in design space: unconventional electronics design through artificial evolution , 1999, IEEE Trans. Evol. Comput..

[4]  Neil W. Bergmann,et al.  Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-on-Chip , 2004, ERSA.

[5]  Apostolos Dollas,et al.  An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems , 2010, IEEE Transactions on Instrumentation and Measurement.

[6]  Andrew M. Tyrrell,et al.  Evolutionary strategies and intrinsic fault tolerance , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[7]  Donatella Sciuto,et al.  A Highly Parallel FPGA-based Evolvable Hardware Architecture , 2009, PARCO.

[8]  David B. Fogel,et al.  Evolutionary Computation: Toward a New Philosophy of Machine Intelligence (IEEE Press Series on Computational Intelligence) , 2006 .

[9]  Adrian Stoica,et al.  Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[10]  Jim Torresen,et al.  An Evolvable Hardware Tutorial , 2004, FPL.

[11]  Jürgen Becker,et al.  A framework for dynamic 2D placement on FPGAs , 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

[12]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[13]  Lukás Sekanina,et al.  A method for design of impulse bursts noise filters optimized for FPGA implementations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[14]  Jürgen Becker,et al.  Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration , 2006, SBCCI '06.

[15]  Tatiana Kalganova,et al.  Bidirectional incremental evolution in extrinsic evolvable hardware , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[16]  Andres Upegui,et al.  Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs , 2005, ICES.

[17]  Andrew M. Tyrrell,et al.  Safe intrinsic evolution of Virtex devices , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[18]  Muhammad Irfan,et al.  Combinational digital circuit synthesis using Cartesian Genetic Programming from a NAND gate template , 2010, 2010 6th International Conference on Emerging Technologies (ICET).

[19]  Cameron Patterson,et al.  JBits™ Design Abstractions , 2001, FCCM.

[20]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[21]  J. Tørresen,et al.  Increased complexity evolution applied to evolvable hardware , 1999 .

[22]  Kyrre Glette,et al.  Evolutionary design of efficient and robust switching image filters , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[23]  Una-May O'Reilly,et al.  GRACE: Generative Robust Analog Circuit Exploration , 2006, EvoWorkshops.

[24]  Neil W. Bergmann,et al.  Evolving FPGA Based Cellular Automata , 1998, SEAL.

[25]  Lukás Sekanina,et al.  Evaluation of a New Platform For Image Filter Evolution , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[26]  Tatiana Kalganova,et al.  Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[27]  Hitoshi Iba,et al.  Evolving hardware with genetic learning: a first step towards building a Darwin machine , 1993 .

[28]  Andres Upegui,et al.  Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[29]  Donatella Sciuto,et al.  HERA: Hardware evolution over reconfigurable architectures , 2011, 2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE).

[30]  Adrian Thompson,et al.  An Evolved Circuit, Intrinsic in Silicon, Entwined with Physics , 1996, ICES.

[31]  Lukás Sekanina,et al.  An Evolvable Combinational Unit for FPGAs , 2004, Comput. Artif. Intell..

[32]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[33]  C. Patterson,et al.  JBits™ Design Abstractions , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[34]  Garrison W. Greenwood,et al.  Introduction to Evolvable Hardware - A Practical Guide for Designing Self-Adaptive Systems , 2006 .

[35]  Lorenz Huelsbergen,et al.  Evolving oscillators in silico , 1999, IEEE Trans. Evol. Comput..

[36]  J. Czerniak,et al.  Application of rough sets in the presumptive diagnosis of urinary system diseases , 2003 .

[37]  Kunle Olukotun,et al.  The Future of Microprocessors , 2005, ACM Queue.

[38]  Kyrre Glette,et al.  Intermediate Level FPGA Reconfiguration for an Online EHW Pattern Recognition System , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[39]  Moritoshi Yasunaga,et al.  Gene Finding Using Evolvable Reasoning Hardware , 2003, ICES.

[40]  D. B. Vernekar,et al.  Reconfigurable FPGA using genetic algorithm , 2010, ICWET.

[41]  Moritoshi Yasunaga,et al.  On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[42]  Adrian Thompson,et al.  On the Automatic Design of Robust Electronics Through Artificial Evolution , 1998, ICES.

[43]  Lukás Sekanina,et al.  Evolutionary functional recovery in virtual reconfigurable circuits , 2007, JETC.

[44]  Andres Upegui,et al.  The Perplexus bio-inspired reconfigurable circuit , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[45]  Julian F. Miller Chapter 18 – The Genetic Algorithm as a Discovery Engine: Strange Circuits and New Principles , 2002 .

[46]  Jim Tørresen,et al.  High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

[47]  Thomas Bäck,et al.  Evolutionary computation: Toward a new philosophy of machine intelligence , 1997, Complex..

[48]  Scott Hauck,et al.  Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation , 2007 .

[49]  Marco D. Santambrogio,et al.  A direct bitstream manipulation approach for Virtex4-based evolvable systems , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[50]  Peter J. Bentley,et al.  Development brings scalability to hardware evolution , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[51]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[52]  Hugo de Garis,et al.  EVOLVABLE HARDWARE Genetic Programming of a Darwin Machine , 1993 .

[53]  Kotagiri Ramamohanarao,et al.  DeEPs: A New Instance-Based Lazy Discovery and Classification System , 2004, Machine Learning.

[54]  Tatiana Kalganova,et al.  FPGA-based Systems for Evolvable Hardware , 2007 .

[55]  Chun-Hsian Huang,et al.  Reconfigurable System Design and Verification , 2009 .

[56]  Stuart J. Russell,et al.  Experimental comparisons of online and batch versions of bagging and boosting , 2001, KDD '01.

[57]  Seda Ogrenci Memik,et al.  Placement and Floorplanning in Dynamically Reconfigurable FPGAs , 2010, TRETS.

[58]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[59]  Paul J. Layzell,et al.  A New Research Tool for Intrinsic Hardware Evolution , 1998, ICES.

[60]  D SantambrogioMarco,et al.  On the Evolution of Hardware Circuits via Reconfigurable Architectures , 2012 .

[61]  Steven A. Guccione,et al.  GeneticFPGA: evolving stable circuits on mainstream FPGA devices , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[62]  Walter Stechele,et al.  Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems , 2010, ARC.

[63]  Julian Francis Miller,et al.  Aspects of Digital Evolution: Evolvability and Architecture , 1998, PPSN.

[64]  Jin Wang,et al.  Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel , 2007, ICES.