Integrated Test Scheme for Digital Signal Processor

Based on boundary scanning and a full scanning structure design of a 16-bit digital signal processor, different test logarithms are used for difference functional parts. The instruction test emphasizes a δ~+ and δ~- fault model. The test instructions are given in the following order. A couple of writing and reading instructions are tested first before other instructions. Pipeline instructions are tested based on the principle of 'write after read' in a data-dependent, condition-dependent, and sequence control dependent fashion. Interruption section is tested on the full scan using an interruption (algorithm.) Data transfer fault test is also considered. MARCH B algorithm is used to test ROM and RAM on the boundary scan. The test scheme of the entire digit signal processor including detailed procedures examples and statistical results of the entire procedures is given.