Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures

By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in differentmodes of the systems can share resources. In this paper, we discuss the architectural issues to design such reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to aggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to place streaming application at runtime which not only considers the placement and communication constraints, but also allows to place merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip. Furthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach.

[1]  Jürgen Teich,et al.  Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures , 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

[2]  Haibo Wang,et al.  A novel approach to minimizing reconfiguration cost for LUT-based FPGAs , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[3]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[4]  Jürgen Teich,et al.  A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs , 2009, FPGA '09.

[5]  Wayne Luk,et al.  Automating production of run-time reconfigurable designs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[6]  Jürgen Teich,et al.  Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras , 2010, ATC.

[7]  Mario Porrmann,et al.  Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs , 2007, ERSA.

[8]  Hartmut Schmeck,et al.  RMB-a reconfigurable multiple bus network , 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.

[9]  Christian Haubelt,et al.  Efficient Reconfigurable On-Chip Buses for FPGAs , 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

[10]  Jürgen Teich,et al.  ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[11]  Jürgen Teich,et al.  Symbolic design space exploration for multi-mode reconfigurable systems , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[12]  Majid Sarrafzadeh,et al.  Area-efficient instruction set synthesis for reconfigurable system-on-chip designs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[13]  Markus Rullmann,et al.  Design Methods and Tools for Improved Partial Dynamic Reconfiguration , 2010, Dynamically Reconfigurable Systems.

[14]  Jürgen Teich,et al.  A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[15]  Oliver Diessel,et al.  On the placement and granularity of FPGA configurations , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).