An efficient power reduction technique for CMOS flash analog-to-digital converters
暂无分享,去创建一个
[1] Asad A. Abidi,et al. A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS , 2001 .
[2] A. Abidi,et al. A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[3] M. Vertregt,et al. A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .
[4] Kyusun Choi,et al. A power and resolution adaptive flash analog-to-digital converter , 2002, ISLPED '02.
[5] Maarten Vertregt,et al. Systematic power reduction and performance analysis of mismatch limited ADC designs , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[6] Yuh-Shyan Hwang,et al. New power saving design method for CMOS flash ADC , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..
[7] Kyusun Choi,et al. “The CMOS Inverter” as a Comparator in ADC Designs , 2004 .
[8] K. Uyttenhove,et al. A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS , 2003, IEEE J. Solid State Circuits.
[9] S. Pavan,et al. A Distortion Compensating Flash Analog-to-Digital Conversion Technique , 2006, IEEE Journal of Solid-State Circuits.
[10] Jun Terada,et al. 8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).
[11] M. Vertregt,et al. A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[12] Tatsuji Matsuura,et al. Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use , 2006, IEICE Trans. Electron..