Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named eSiFO technology was reported. For eSiFO package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An eSiFO package with size of 3.3×3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of eSiFO was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, eSiFO has lower thermal stress than FOWLP using EMC.
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