Security Metrics for Power Based SCA Resistant Hardware Implementation

Power based side-channel attacks (SCA) are well-known major threats to cryptographic devices such as smart cards or other embedded systems. Quantification of resistance or robustness of a cryptographic device against power based SCA is needed as part of the VLSI CAD design flow. The security metric used in such a quantification can be included in design constraints and optimizations just like area and delay. We investigate two SCA security metrics: (1) Kullback-Leibler divergence and (2) mutual information. These metrics are applicable at multiple design abstraction levels from logic level, net list level to layout level. If the implementation at some abstraction level does not satisfy the threshold of the SCA metric, it should be transformed until the SCA metric value is acceptable. However, computation of these metrics is significantly challenging. We propose a relatively fast logic level SCA analysis with renewal process and linear regression methodology. This fast test can be used as a first level filter for SCA vulnerability. Mutual information computation requires building more significant statistical model which involves multiple power simulations. The mutual information based SCA analysis can be exploited for more realistic and accurate verification at the physical transistor or layout level.